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atomic.fence validation and binary encoding #140
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I don't quite understand why fence is allowed to be used with non-shared memories but other atomic instructions are not. Can you elaborate on that a bit? |
@tlively, a fence is not tied to any memory, but commits all accesses (which may involve multiple memories or even other state than memories in the future) that have occurred in the thread (which may include accesses perfomed in other modules on the same thread). So it isn't meaningful to require a specific memory to be present locally. |
I think this makes sense. The same point holds for other atomic operations - any |
Yes, I assumed we would use the memarg immediate for other orderings in the future. We may want to use a single 0 byte for |
@rossberg, I buy that a fence commits all accesses, even on a single thread, and I think that is a good argument for allowing it in modules without shared memories. But by extension of the same reasoning shouldn't all other atomic operations be allowed in these modules as well? They could still have their ordering guarantees on a single thread, they just wouldn't be as useful. Also, I still don't quite see how a fence on a single thread would be useful. Can you give me an example where a single-threaded program could be observably different if it included a fence? |
@tlively, all other atomic operators operate on a specific memory -- via the memory index 0 that is currently implicit in the instruction but may be explicit once we allow multiple memories. So memory 0 needs to exist in the module. A fence doesn't have any effect in a single-threaded program. However, my point was that it still has an effect on everything in the same thread in a multi-threaded program. Consider:
Imagine you instantiate both |
Just to make @rossberg's example completely tight, the load and store in module $A should be release/acquire atomics. I think the disconnect here is that not declaring a shared memory doesn't imply that the module is only going to be used in a single-threaded context - that just happens to be (kind of) true for the instructions we've previously defined. |
@binji would a reasonable encoding be something like memargf ::= 0x00 atomic.fence ::= 0xFE 0x0F m:memargf to keep the convention that (only) atomic memory accesses have a non-zero first nibble, but thematically positioning fence as close as possible to them (and leaving no gap)? |
@conrad-watt that looks right to me, though I think we'd just inline the |
This adds decoding and compilation of the "atomic.fence" operator, which is intended to preserve the synchronization guarantees of higher-level languages. Unlike other atomic operators, it does not target a particular linear memory. It may occur in modules which declare no memory, or a non-shared memory, without causing a validation error. See proposal: WebAssembly/threads#141 See discussion: WebAssembly/threads#140 R=clemensh@chromium.org TEST=cctest/test-run-wasm-atomics/RunWasmXXX_AtomicFence BUG=v8:9452 Change-Id: Ibf7e46227f7edfe5c81c097cfc15924c59614067 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1701856 Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Clemens Hammacher <clemensh@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#62821}
port 4ca8b4d https://crrev.com/c/1701856 Original Commit Message: This adds decoding and compilation of the "atomic.fence" operator, which is intended to preserve the synchronization guarantees of higher-level languages. Unlike other atomic operators, it does not target a particular linear memory. It may occur in modules which declare no memory, or a non-shared memory, without causing a validation error. See proposal: WebAssembly/threads#141 See discussion: WebAssembly/threads#140 Change-Id: Ia60d58a6bf58e8236591d515d30184418cee47c5 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1710337 Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Yu Yin <xwafish@gmail.com> Cr-Commit-Position: refs/heads/master@{#62843}
Port 4ca8b4d Original Commit Message: This adds decoding and compilation of the "atomic.fence" operator, which is intended to preserve the synchronization guarantees of higher-level languages. Unlike other atomic operators, it does not target a particular linear memory. It may occur in modules which declare no memory, or a non-shared memory, without causing a validation error. See proposal: WebAssembly/threads#141 See discussion: WebAssembly/threads#140 R=mstarzinger@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com BUG=v8:9452 LOG=N Change-Id: Ib8ad24e65154d7555a47e537f81110be47f4d4de Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1710620 Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Reviewed-by: Junliang Yan <jyan@ca.ibm.com> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#62850}
This commit implements the 'atomic.fence' Wasm instruction. Issue: WebAssembly/threads#140 Overview: WebAssembly/threads#141 The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future memory order immediate. The instruction is implemented by emitting a memoryBarrier through the macro assembler. Differential Revision: https://phabricator.services.mozilla.com/D39264 --HG-- extra : moz-landing-system : lando
This commit implements the 'atomic.fence' Wasm instruction. Issue: WebAssembly/threads#140 Overview: WebAssembly/threads#141 The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future memory order immediate. The instruction is implemented by emitting a memoryBarrier through the macro assembler. Differential Revision: https://phabricator.services.mozilla.com/D39264
This commit implements the 'atomic.fence' Wasm instruction. Issue: WebAssembly/threads#140 Overview: WebAssembly/threads#141 The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future memory order immediate. The instruction is implemented by emitting a memoryBarrier through the macro assembler. Differential Revision: https://phabricator.services.mozilla.com/D39264 UltraBlame original commit: d32c27f13f21b0927cbfb7ce6f8509c0dea6bf09
This commit implements the 'atomic.fence' Wasm instruction. Issue: WebAssembly/threads#140 Overview: WebAssembly/threads#141 The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future memory order immediate. The instruction is implemented by emitting a memoryBarrier through the macro assembler. Differential Revision: https://phabricator.services.mozilla.com/D39264 UltraBlame original commit: d32c27f13f21b0927cbfb7ce6f8509c0dea6bf09
This commit implements the 'atomic.fence' Wasm instruction. Issue: WebAssembly/threads#140 Overview: WebAssembly/threads#141 The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future memory order immediate. The instruction is implemented by emitting a memoryBarrier through the macro assembler. Differential Revision: https://phabricator.services.mozilla.com/D39264 UltraBlame original commit: d32c27f13f21b0927cbfb7ce6f8509c0dea6bf09
This commit implements the 'atomic.fence' Wasm instruction. Issue: WebAssembly/threads#140 Overview: WebAssembly/threads#141 The instruction is encoded as, 0xFE 0x03, with a reserved byte trailing for a future memory order immediate. The instruction is implemented by emitting a memoryBarrier through the macro assembler. Differential Revision: https://phabricator.services.mozilla.com/D39264
After the last CG, we agreed to add atomic.fence.
Validation-wise, the instruction has type ([] -> []). Unlike other atomic.* instructions, it is not a validation error for the instruction to occur in a module with a non-shared memory. This is because the instruction fences all memories in the store, not just that of the current module.
Encoding-wise, I hope someone with better intuition about the binary format can suggest something.
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