Fix dclk parent clock for hdmi vop0

Fix dclk parent for hdmi vop0 to solve tty terminal out of screen, and with the default parent clock, most dclk divisions are not available for many resolutions.
This problem can be reproduced on some screens that are not 1080p or 720p, etc.

Before fix with same monitor:
```
root@orangepi5:/boot/dtb/rockchip# cat /sys/kernel/debug/clk/clk_summary | grep "hdmiphy" -A 1
       clk_hdmiphy_pixel0             1        2        0   148500000          0     0  50000
       usb480m_phy3                   2        4        0   480000000          0     0  50000
root@orangepi5:/boot/dtb/rockchip# cat /sys/class/drm/card0-HDMI-A-1/modes 
1920x1080
1280x1024
1280x720
800x600
720x480
720x480
```

After fix with same monitor:
```
root@orangepi5:/home/orangepi/office/mhz# cat /sys/kernel/debug/clk/clk_summary | grep "hdmiphy" -A 1
       clk_hdmiphy_pixel0             2        3        0   106500000          0     0  50000
          dclk_vop0                   2        4        0   106500000          0     0  50000
root@orangepi5:/boot/dtb/rockchip# cat /sys/class/drm/card0-HDMI-A-1/modes 
1440x900
1920x1080
1920x1080
1280x1024
1280x1024
1280x720
1280x720
1024x768
1024x768
800x600
800x600
720x480
720x480
720x480
640x480
640x480
640x480
720x400
```

We can see page 47 of the "Rockchip_Developer_Guide_DRM_Display_Driver_CN.pdf" document v3.5.1 for details :
```
The features of hdmi_phy0_pll, hdmi_phy1_pll are as follows.
1. Supports arbitrary crossover
2. Exclusive PLL for VOP when HDMI is not in operation, shared PLL with HDMI PHY when HDMI is in operation
The PLL on the PHY can not be used by the VOP when the EDP is in operation.

For dclk_vp0/1/2, one of hdmi_phy0_pll, hdmi_phy1_pll, or dclk_vpx_src0/1/2 can be specified as its parent clock, and for dclk_vpx_src0/1/2, one of hdmi_phy0_pll, hdmi_phy1_pll, or dclk_vpx_src0/1/2 can be specified as its parent clock.
specify
V0PLL, CPLL, GPLL, AUPLL as its parent clock.
For dclk_vp3, you can specify one of V0PLL, CPLL, GPLL, AUPLL as its parent clock.
V0PLL, CPLL, GPLL, AUPLL are the PLLs on the system CRU, hdmi_phy0_pll and hdmi_phy1_pll are the PLLs on the HDMI PHY
The characteristics of VOPLL are as follows.
1. VOP exclusive PLLs 2.
2. supports arbitrary frequencies
3. default binding to dclk_vp2 in dts, codes such as
The characteristics of CPLL, GPLL, AUPLL are as follows
1. shares the PLL with other IP modules 2.
2. does not support arbitrary dividing, the output frequency is an integer division of the PLL frequency
3. dclk_vp0/1/3 is tied to the GPLL by default
```

To be tested (missing screen, cannot be tested)
1. 8K resolution output (was able to test after I contacted OrangePi officials)
2. Multi-screen display

patch/kernel/rockchip-rk3588-legacy/2008-fix-dclk-parent-clock-for-hdmi-vop0.patch

@@ -0,0 +1,14 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
+index 28ad1d366..26531d5ac 100755
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
+@@ -594,3 +594,9 @@ &vp3 {
+ 	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
+ 	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
+ };
++
++/* Fix tty terminal out of screen, and most dclk of resolutions was not supported in hdmiphy clock from parent clock by default */
++&display_subsystem {
++	clocks = <&hdptxphy_hdmi_clk0>;
++	clock-names = "hdmi0_phy_pll";
++};