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RISC-V Matrix Multiplication Extension Specification v0.3.0
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@QJtaibai QJtaibai released this 02 Jun 08:30
· 17 commits to master since this release
v0.3.0
bdca7a2

RISC-V Matrix Multiplication Extension Specification v0.3.0
Update log compared to v0.1.0：

  • Add widen floating-point matrix multiplication instructions for mixed precision

  • Add move instruction between scalar registers and matrix registers for debug purpose

  • Change mrelease to initial ms status/add mzero for security issues

  • Remove streaming memory access instruction, Compatible with zhintntl extensions instead of customizing hint operations in extensions

  • Support new data types int4/bf16

  • Add RLEN, modify MLEN definition for a clearer programming model

  • Reorganize the matrix CSR to be more accurate and meet the RISC-V standards

  • Modify arithmetic instructions opcode, more consistent with RISC-V coding habits

  • New intrinsic style with function overloading

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