Updates for Vitis AI 1.0 release

AI-Model-Zoo/get_model.sh

@@ -1,20 +1,20 @@
 #!/bin/bash
 
 
-wget https://www.xilinx.com/bin/public/openDownload?filename=all_models.zip
-mv openDownload?filename=all_models.zip all_models.zip
-check_result=`md5sum -c <<<"0fc242102699cad110027ecfff453d91 all_models.zip"`
+wget https://www.xilinx.com/bin/public/openDownload?filename=all_models_1.0.zip
+mv openDownload?filename=all_models_1.0.zip all_models_1.0.zip
+check_result=`md5sum -c <<<"ed5509bcd0ce5e3aa2b220145acc17f5 all_models_1.0.zip"`
 #echo $check_result
 
-if [ "$check_result" != "all_models.zip: OK" ]; then
+if [ "$check_result" != "all_models_1.0.zip: OK" ]; then
    echo "md5sum check failed! Please try to download again."
    exit 1
 else
    if [ `command -v unzip` ]; then
-      unzip all_models.zip -d models
+      unzip all_models_1.0.zip -d models
    else 
       sudo apt install unzip
-      unzip all_models.zip -d models
+      unzip all_models_1.0.zip -d models
    fi  
    echo "all models downloaded successfully."
    exit 0

DPU-TRD/README.md

@@ -1,5 +1,66 @@
-DPU V3.1
+# Zynq UltraScale＋ MPSoC DPU TRD
+
+The Xilinx Deep Learning Processor Unit(DPU) is a configurable computation engine dedicated for convolutional neural networks. The degree of parallelism utilized in the engine is a design parameter and application. It includes a set of highly optimized instructions, and supports most convolutional neural networks, such as VGG, ResNet, GoogleNet, YOLO, SSD, MobileNet, FPN, and others.
+
+### Features
+
+- One AXI salve interface for accessing configuration and status registers.
+
+- One AXI master interface for accessing instructions.
+
+- Supports configurable AXI master interface with 64 or 128 bits for accessing data depending on the target device.
+
+- Supports individual configuration of each channel.
+
+- Supports optional interrupt requeset generation.
+
+- Some highlights of DPU functionality include:
+	- Configurable hardware architecture includes: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096
+	- Maximum of three cores
+	- Convolution and deconvolution
+	- Depthwise convolution
+	- Max poolling
+	- Average poolling
+	- ReLU, RELU6, and Leaky ReLU
+	- Concat
+	- Elementwise-sum
+	- Dilation
+	- Reorg
+	- Fully connected layer
+	- Softmax
+	- Bach Normalization
+	- Split
+
+### Hardware Architecture
+
+The detailed hardware architecture of the DPU is shown in the following figure. After start-up, the DPU fetches instructions from off-chip memory to control the operation of the computing engine. The instructions are generated by the DNNC where substantial optimizations have been performed. On-chip memory is used to buffer input, intermediate, and output data to achieve high throughput and efficiency. The data is reused as much as possible to reduce the memory bandwidth. A deep pipelined design is used for the computing engine. The processing elements (PE) take full advantage of the finegrained building blocks such as multipliers, adders and accumulators in Xilinx devices.
+
+![DPU Hardware Architecture](./prj/Vitis/doc/dpu_hardware_arch.png)
+
+
+There are three dimensions of parallelism in the DPU convolution architecture - pixel parallelism, input channel parallelism, and output channel parallelism. The input channel parallelism is always equal to the output channel parallelism. The different architectures require different programmable logic resources. The larger architectures can achieve higher performance with more resources. The parallelism for the different architectures is listed in the table.
+
+|Connolution Architecture|Pixel Parallelism(PP)|Input Channel Parallelism(ICP)|Output Channel Parallelism(OCP)|Peak(operations/per clock)|
+|:---|:---|:---|:---|:---|
+|B512|4|8|8|512|
+|B800|4|10|10|800|
+|B1024|8|8|8|1024|
+|B1152|4|12|12|1152|
+|B1600|8|10|10|1600|
+|B2304|8|12|12|2304|
+|B3136|8|14|14|3136|
+|B4096|8|16|16|4096|
+
+
+****
+
+[DPU TRD Vitis Flow](./prj/Vitis/README.md)
+
+****
+
+The Vivado flow will come soon.
+
+****
+
 
-For the Vitis flow, go to <a href="prj/Vitis">prj/Vitis</a>.
 
-The Vivado flow is coming soon.

DPU-TRD/prj/Vitis/README.md

@@ -64,9 +64,10 @@ Required:
   - install the Vitis 2019.2.[Vitis Core Development Kit](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html) 
   - [Silicon Labs quad CP210x USB-to-UART bridge driver](http://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx)
   - Serial terminal emulator e.g. [teraterm](http://logmett.com/tera-term-the-latest-version)
-  - install the xrt drivers. [xrt](https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#gettingStarted)  
-  - install the zcu102 base platform. [zcu102 base](https://gitenterprise.xilinx.com/swm/Vitis_Embedded_Platform_Source/tree/master/Xilinx_Official_Platforms/zcu102_base)
-  - The matching DNNDK version is VAI1.0
+  - install [XRT 2019.2](https://github.com/Xilinx/XRT/tree/2019.2)
+  - install [zcu102 base platform](https://www.xilinx.com/member/forms/download/design-license-xef.html?filename=zcu102_base_2019.2.zip)
+  - install [Vitis AI 1.0](https://github.com/Xilinx/Vitis-AI) to run models other than Resnet50, Optional 
+  - install [Vitis AI Library 1.0](https://github.com/Xilinx/Vitis-AI/Vitis-AI-Library) to configure DPU in Vitis AI Library ZCU102 and ZCU104 pacakge, Optional
 
 ------
 
@@ -196,7 +197,7 @@ After the linux boot, Run:
 ```
 
 
-###### **Note:** If you want to run other network. Please refer to the [DNNDK](https://www.xilinx.com/products/design-tools/ai-inference/ai-developer-hub.html#edge)
+###### **Note:** If you want to run other network. Please refer to the [Vitis AI Github](https://github.com/Xilinx/Vitis-AI) and [Vitis AI User Guide](???).
 
 
 ### 5.3 Change the Configuration
@@ -206,7 +207,7 @@ The DPU IP provides some user-configurable parameters to optimize resource utili
 
 The TRD also support the softmax function.
 
-More details about the DPU. [DPU](https://www.xilinx.com/support/documentation/ip_documentation/dpu/v2_0/pg338-dpu.pdf#nameddest=xDPUTRDOverview)
+For more details about the DPU, please read [DPU IP Product Guide](https://www.xilinx.com/support/documentation/ip_documentation/dpu/v3_0/pg338-dpu.pdf)
 
 
 #### 5.3.1 Set the DPU Core Number
@@ -402,9 +403,9 @@ If you meet some timing issues. you can modify the [vivado] part of prj_config f
 
 ------
 
-### 5.5 Integrate the DPU for zcu102 and zcu104 AI-SDK release
+### 5.5 Integrate the DPU for Vitis AI Library release
 
-This chapter introduces how to configue the project for the zcu102 and zcu104 AI-SDK released package.
+This chapter introduces how to configue the project for [Vitis AI Library](https://github.com/Xilinx/Vitis-AI/Vitis-AI-Library) released package for ZCU102 and ZCU104.
 
 #### 5.5.1 Configue the zcu102 released project
 

Vitis-AI-Library/README.md

@@ -1,8 +1,20 @@
-Vitis AI Library v1.0
-======================
+<table width="100%">
+  <tr width="100%">
+    <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Vitis AI Library v1.0</h1>
+    </td>
+ </tr>
+ </table>
+
+# Introduction
+The Vitis AI Library is a set of high-level libraries and APIs built for efficient AI inference with Deep-Learning Processor Unit (DPU). It is built based on the Vitis AI Runtime with Unified APIs, and it fully supports XRT 2019.2.
+
+The Vitis AI Library provides an easy-to-use and unified interface by encapsulating many efficient and high-quality neural networks. This simplifies the use of deep-learning neural networks, even for users without knowledge of deep-learning or FPGAs. The Vitis AI Library allows users to focus more on the development of their applications, rather than the underlying hardware.
 
 Please check <https://www.xilinx.com/products/design-tools/ai-inference/ai-developer-hub.html#edge> for updates.
 
+<p align="center">
+  <img src="ai_library_diagram.png" >
+</p>
 
 Vitis AI Library directory structure introduction
 --------------------------------------------------
@@ -49,3 +61,118 @@ vitis_ai_library
     ├── yolov2
     └── yolov3
 ```
+
+## Quick Start
+### Setting Up the Host
+1. Download the vitis-ai-docker-runtime image from https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html
+
+2. Set up the docker runtime system according to the docker installation document.
+```
+   $sh docker_run.sh
+```
+3. Copy or git clone the AI Library package to the `workspace` folder.
+
+4. Cross compile the demo in the AI Library, using yolov3 as example.
+```
+$cd /workspace/vitis_ai_library_r1.0/demo/yolov3
+$sh -x build.sh
+```	
+
+5. To compile the library sample in the AI Library, take classification for example, execute the following command.
+```
+$cd /workspace/vitis_ai_library_r1.0/samples/classification
+$sh -x build.sh
+```	
+
+6. To modify the library source code, view and modify them under `/workspace/vitis_ai_library_r1.0/libsrc`.
+   If you want to recompile the library, take libdpclassification for example, execute the following command:
+```
+$cd /workspace/vitis_ai_library_r1.0/libsrc/libdpclassification
+$sh -x build.sh
+```
+
+### Setting Up the Target
+
+1. Installing a Board Image.
+	* Download the SD card system image files from the following links:  
+
+		[ZCU102](https://www.xilinx.com/bin/public/openDownload?filename=xilinx-zcu102-dpu-v2019.2.img.gz)  
+
+		[ZCU104](https://www.xilinx.com/bin/public/openDownload?filename=xilinx-zcu102-dpu-v2019.4.img.gz)  
+
+      	Note: The version of the board image should be 2019.2 or above.
+	* Use Win32DiskImager (free opensource software) to burn the image file onto the SD card.
+	* Insert the SD card with the image into the destination board.
+	* Plug in the power and boot the board using the serial port to operate on the system.
+	* Set up the IP information of the board using the serial port.
+	You can now operate on the board using SSH.
+
+2. Installing AI Model Package   
+	* Download [ZCU102 AI Model](https://www.xilinx.com/bin/public/openDownload?filename=vitis_ai_model_ZCU102_2019.2-r1.0.deb)  
+
+		You can also download [ZCU104 AI Model](https://www.xilinx.com/bin/public/openDownload?filename=vitis_ai_model_ZCU102_2019.2-r1.0.deb) if you use ZCU104 
+
+	* Copy the downloaded file to the board using scp with the following command.
+	```
+	  $scp vitis_ai_model_ZCU102_2019.2-r1.0.deb root@IP_OF_BOARD:~/
+	```
+	* Log in to the board (usong ssh or serial port) and install the model package.
+	* Run the following command.
+	```
+	  #dpkg -i vitis_ai_model_ZCU102_2019.2-r1.0.deb
+	```
+
+3. Installing AI Library Package
+	* Download the [Vitis AI Library 1.0](https://www.xilinx.com/bin/public/openDownload?filename=vitis_ai_library_2019.2-r1.0.deb)  
+	* Download the [demo video files](https://www.xilinx.com/bin/public/openDownload?filename=vitis_ai_library_r1.0_video.tar.gz) and untar into the corresponding directories  
+
+	* Copy the downloaded file to the board using scp with the following command.
+	```
+	  $scp vitis_ai_library_2019.2-r1.0.deb root@IP_OF_BOARD:~/
+	```
+	* Log in to the board using ssh. You can also use the serial port to login.
+	* Install the Vitis AI Library.
+	```
+	  #dpkg -i vitis_ai_library_2019.2-r1.0.deb
+	```
+	  
+### Running Vitis AI Library Examples
+
+1. Enter the extracted directory of example in target board.
+	```
+	#cd /usr/share/vitis_ai_library/samples/facedetect
+	```
+
+2. Run the image example.
+	```
+	#./test_jpeg_facedetect densebox_640_360 sample_facedetect.jpg
+	```
+
+3. Run the video example.
+```
+	#./test_video_facedetect densebox_640_360 video_input.mp4 -t 8
+	Video_input.mp4: The video file's name for input.The user needs to prepare the videofile.
+	-t: <num_of_threads>
+```
+
+4. To test the program with a USB camera as input, run the following command:
+```
+	#./test_video_facedetect densebox_640_360 0 -t 8
+	0: The first USB camera device node. If you have multiple USB camera, the value might be 1,2,3 etc.
+	-t: <num_of_threads>
+```
+
+5. To test the performance of model, run the following command:
+```
+	#./test_performance_facedetect densebox_640_360 test_performance_facedetect.list -t 8 -s 60
+	-t: <num_of_threads>
+	-s: <num_of_seconds>
+```
+
+6. To check the version of Vitis AI Library, run the following command:
+```
+	#vitis_ai
+```	
+
+
+

Vitis-AI-Library/demo/classification/build.sh

@@ -1,50 +1,4 @@
-#
-# (c) Copyright 2018 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-#/bin/sh
+#!/bin/bash
+
 CXX=${CXX:-g++}
 $CXX -std=c++11 -O3 -I. -o demo_classification demo_classification.cpp -lopencv_core -lopencv_video -lopencv_videoio -lopencv_imgproc -lopencv_imgcodecs -lopencv_highgui -lglog -ldpbase -ldpproto -lvitis_dpu