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When is .run_summary file generated? #138

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m-kru opened this issue Dec 4, 2021 · 5 comments
Closed

When is .run_summary file generated? #138

m-kru opened this issue Dec 4, 2021 · 5 comments
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@m-kru
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m-kru commented Dec 4, 2021

Part5 mentions .run_summary file. However, after successful build of the kernel with Vitis 2020.2 there is no file with .run_summary extension. What program is responsible for generating this file, and when exactly (at which step) this file should be created?

@m-kru m-kru changed the title When is .run_summary generated When is .run_summary file generated? Dec 4, 2021
@randyh62
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The run_summary is generated when the application/xclbin is run and when the opencl_summary and opencl_trace is specified, or other appropriate options are specified, in the xrt.ini file. It is generated when the application is run, not when it is built. The compile_summary and link_summary are generated when the kernels and xclbin are built.

@m-kru
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m-kru commented Dec 10, 2021

@randyh62 Is run_summary generated also when opencl is not used, solely xrt?

@randyh62
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@andy39866821
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andy39866821 commented Apr 12, 2022

Hi,
I place xrt.ini in both hw/ and hw_emu/, but xrt.run_aummary didn't generate.
I doesn't modify source code (host.cpp, vadd.cpp, etc.)
Here are the commands and files I used with U50.
Is there any wrong I made?

cd hw_emu
g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++
emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1
v++ -c -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ../../src/u50.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo 
v++ -l -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ../../src/u50.cfg ./vadd.xo -o vadd.xclbin

setenv XCL_EMULATION_MODE hw_emu
./app.exe

xrt.ini

[Debug]
opencl_summary=true
opencl_trace=true

u50.cfg

debug=1
save-temps=1

[connectivity]
nk=vadd:1:vadd_1
sp=vadd_1.in1:HBM[1]
sp=vadd_1.in2:HBM[2]
sp=vadd_1.out:HBM[1]

[profile]
data=all:all:all

@randyh62
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Hi andy39866821,

I ran the hw_emu build just to see if it worked. I ran essentially the same commands as you, and used your u50.cfg file and your xrt.ini file contents. It worked fine and generated the xrt.run_summary file as expected. The comparison of your commands and my commends are below, though I did not see an obvious error in your commands.


ANDY: g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++
RANDY: g++ -Wall -g -std=c++11 /Vitis-Tutorials/Getting_Started/Vitis/example/src/host.cpp -o hw_emu/app.exe
-I/opt/xilinx/xrt/include/ -L/opt/xilinx/xrt/lib/ -lOpenCL -pthread -lrt -lstdc++

ANDY: emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1
RANDY: emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --od hw_emu --nd 1

ANDY: v++ -c -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ../../src/u50.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo
RANDY: v++ -c -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ./u50.cfg -k vadd -I/Vitis-Tutorials/Getting_Started/Vitis/example/src
/Vitis-Tutorials/Getting_Started/Vitis/example/src/vadd.cpp -o hw_emu/vadd.xo

ANDY: v++ -l -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ../../src/u50.cfg ./vadd.xo -o vadd.xclbin
RANDY: v++ -l -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ./u50.cfg hw_emu/vadd.xo -o hw_emu/vadd.xclbin

ANDY: setenv XCL_EMULATION_MODE hw_emu
./app.exe
RANDY: cp xrt.ini hw_emu
cd hw_emu && XCL_EMULATION_MODE=hw_emu ./app.exe

INFO: Found Xilinx Platform
INFO: Loading 'vadd.xclbin'
INFO: [HW-EMU 01] Hardware emulation runs simulation underneath. Using a large data set will result in long simulation times. It is recommended that a small dataset is used for faster execution. The flow uses approximate models for Global memories and interconnect and hence the performance data generated is approximate.
configuring penguin scheduler mode
scheduler config ert(0), dataflow(1), slots(16), cudma(1), cuisr(0), cdma(0), cus(1)
TEST PASSED
INFO::[ Vitis-EM 22 ] [Time elapsed: 0 minute(s) 16 seconds, Emulation time: 0.0784974 ms]
Data transfer between kernel(s) and global memory(s)
vadd_1:m_axi_aximm1-HBM[1] RD = 16.000 KB WR = 16.000 KB
vadd_1:m_axi_aximm2-HBM[2] RD = 16.000 KB WR = 0.000 KB

/Vitis-Tutorials/Getting_Started/Vitis/example/u50> ll hw_emu/
total 63M
-rwxr-xr-x 1 randyh hd 542K Apr 12 20:08 app.exe
-rw-r--r-- 1 randyh hd 769 Apr 12 20:08 emconfig.json
-rw-r--r-- 1 randyh hd 769 Apr 12 20:17 emulation_debug.log
-rw-r--r-- 1 randyh hd 5.8K Apr 12 20:17 opencl_trace.csv
-rw-r--r-- 1 randyh hd 5.2K Apr 12 20:17 summary.csv
-rw-r--r-- 1 randyh hd 62M Apr 12 20:17 vadd.xclbin
-rw-r--r-- 1 randyh hd 9.4K Apr 12 20:17 vadd.xclbin.info
-rw-r--r-- 1 randyh hd 29K Apr 12 20:17 vadd.xclbin.link_summary
-rw-r--r-- 1 randyh hd 197K Apr 12 20:10 vadd.xo
-rw-r--r-- 1 randyh hd 7.2K Apr 12 20:10 vadd.xo.compile_summary
-rw-r--r-- 1 randyh hd 34K Apr 12 20:17 xilinx_u50_gen3x16_xdma_201920_3-0-vadd_simulate.log
-rw-r--r-- 1 randyh hd 944 Apr 12 20:17 xilinx_u50_gen3x16_xdma_201920_3-0-vadd_xsc_report.log
-rw-r--r-- 1 randyh hd 46 Apr 12 20:17 xrt.ini
-rw-r--r-- 1 randyh hd 562 Apr 12 20:17 xrt.run_summary

CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
9750b9b Merge pull request Xilinx#142 from mlechtan/next
daf8329 Fix for CR-1110410, fix for FFT's heap size allocation and dyn stage handling.
349cfeb Fix for CR-1112154
ce41c3c Merge pull request Xilinx#5 from FaaSApps/next
b0b3c30 fix_cr-1111508 (Xilinx#141)
100d912 Merge pull request Xilinx#138 from ariea/next
1ced2ce Merge branch 'next' into next
d29cb2b add common resources for HTML reports
2ae6069 add an new case to support gui=true (Xilinx#129)
57c06d3 Merge pull request Xilinx#134 from mlechtan/merge_pr128
892db94 Merge branch 'next' into merge_pr128
543190d Fix for architecture reporting method for FIRs
01287ea Add dsplib QoR harvesting scripts (Xilinx#128)
e277243 update makefiles using updated makefile-generator
2e65fca Merge pull request Xilinx#135 from FaaSApps/crvo3463
614cc5c makefile update uut_out_dir to static dir
0338e3f Revert last commit
34caed6 change uut_out_dir to static dir
a283a95 Merge pull request Xilinx#4 from FaaSApps/next
9a0aca4 get_stats fix
68e2713 FIR Decimate Sym fix to verify crvo3463
2d43b15 update get_stats
6048e65 Fix for architecture reporting.
dac2eb5 Enabling cfloat ptsize=16 to be cascaded
f0419e8 Merge branch 'next' into next
4b2a6d5 update files from create dsplib script
cdb178f Merge pull request Xilinx#132 from mlechtan/next
b76cd67 Merge pull request Xilinx#133 from dbee/next
e39f73b update with new param
7911add makefile updates
603ba07 min theory update
5e026a5 dds updates with streams and cleanup
d84957a add safeguard to get_stats.tcl
8f00a8d remove batch_status.tcl
613e5dc Removing kernel compiler options:  -Xchess=main:noodle.optim.olbb=20 -Xchess=main:backend.mist2.pnll="off"
2a754e0 Fix for CR-1110144 and ADL-696
f36ddc0 Merge pull request #1 from FaaSApps/next
fb08c65 change exit method from diff.tcl to diff_exit.tcl
768dbc1 add license info
b63051e add license info and update makefiles
900b68d remove redundant files
8cbd2dd remove redundant batch_status.tcl script
5153c04 add batch_status directory
3b9c9c7 commit auto-generated files from create_dsplib_zip
4d1741b Merge branch 'next' of https://gitenterprise.xilinx.com/ariea/xf_dsp into next
ee4ec16 Merge branch 'next' of https://gitenterprise.xilinx.com/ariea/xf_dsp into next
ad18675 makefile licenses
446247c Merge pull request Xilinx#3 from FaaSApps/next
e63e0e4 fix revert
67af8a6 add license info
5f1ab0d Merge pull request #2 from FaaSApps/next
c336f9b jenkinsfile fix 5
7b97d92 jenkinsfile fix 4
0cfe02e jenkinsfile fix 3
f68be8d jenkinsfile fix 2
ff3b449 fix jenkinsfile 1
d861796 fix jenkinsfile upstream dependency
162a51e Merge branch 'FaaSApps-next' into next
3dbdc16 Merge branch 'next' of https://gitenterprise.xilinx.com/FaaSApps/xf_dsp into FaaSApps-next
b52830f modify jenkinsfile
76e0dd0 init commit
fdaff02 init commit

Co-authored-by: sdausr <sdausr@xilinx.com>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
2079b9b Ethash SC prototype (Xilinx#150)
c08ada1 merge tutorial (Xilinx#157)
04302db Merge pull request Xilinx#155 from changg/fix_issues
f792a67 revert the change
98ccdea test
8fa693a fix security issues
f60f3c8 Update Makefile (Xilinx#152)
9612886 Fix cr 1114888 1114873 (Xilinx#151)
e622384 update rc4 benchmark case, reduce to 1 kernel (Xilinx#149)
8b43251 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 (Xilinx#145)
3d86755 Fix cr 1114880 1114888 (Xilinx#146)
49d5003 Merge pull request Xilinx#144 from liyuanz/replace_cflags
43651c8 replace cflags with clflags
ee65b70 Add open file failure guard and mode for read-only (Xilinx#143)
a05e213 Merge pull request Xilinx#141 from liyuanz/replace_blacklist
9095130 replace whiltelist/blacklist to allowlist/blocklist
fb7dfd6 Merge pull request Xilinx#137 from leol/fix-CR
4454482 Merge pull request Xilinx#138 from liyuanz/next
ded8552 add mem for mem limit case
80dddf9 Fix for L1 CBC SC benchmarks host build issue
dd68b83 Clang format crc32c_sc.cpp with 3.9.0 version
443fa59 Merge pull request Xilinx#132 from liyuanz/next
34bc727 Merge pull request Xilinx#134 from liyuanz/replace_targets
be250a9 update targes
3e28567 update
e0cbc3d Refine crc32c to improve the performance of the resdu line (Xilinx#133)
884b4f9 update
c790abe update
0256aac update
61cb658 update Makefile and utils.mk
359c5b6 Clang format crc32c_sc.cpp for both 3.9.0 and 8.0.0 (Xilinx#131)
92cf068 SC L3 design of CRC32C (Xilinx#123)
c00352b update Makefile for Vitis Flow testcase (Xilinx#128)
33c3c23 remove ssl linkage from library,json (Xilinx#127)
c67da48 Merge pull request Xilinx#126 from changg/metadata
080686b draft metadata files
e3efd4d add aws support (Xilinx#124)
87f65b0 change 2021.2_stable_latest to 2022.1_stable_latest

Co-authored-by: sdausr <sdausr@xilinx.com>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
0dcda94 Merge pull request Xilinx#144 from tuol/cr_1140424
a76d87e Merge pull request Xilinx#145 from tuol/cr_1140420
cd2dbfd make two benchmark case disable, due to similiar issue with their corresponding cases in tests
35211e8 lower build frequency
331c32b Merge pull request Xilinx#142 from liyuanz/next
28b07ab update mk
9861fbd Merge pull request Xilinx#141 from tuol/cr_1137645
3cee823 add missing header of vector and future
e01e471 Merge pull request Xilinx#140 from tuol/cr_1135038
aeb6da3 fix error in description.json
6f9dea0 Merge pull request Xilinx#137 from yuanqian/update_doc_next_portal
d2fb2df Merge pull request Xilinx#138 from liyuanz/add_mem
2aa1d70 Merge pull request Xilinx#139 from liyuanz/add_mem
390ad14 add mem and time
474e03e update
ca904f2 add mem
66ec334 update doc in next branch for portal
ab09c33 Merge pull request Xilinx#136 from liyuanz/next
3e33b54 update makefile
5fbdc9c Merge pull request Xilinx#134 from changg/22.2_mks
a477498 fix u280
0b9d86c 22.2 mk update
2e27386 change 2022.1_stable_latest to 2022.2_stable_latest

Co-authored-by: sdausr <sdausr@xilinx.com>
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