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When is .run_summary file generated? #138
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The run_summary is generated when the application/xclbin is run and when the opencl_summary and opencl_trace is specified, or other appropriate options are specified, in the xrt.ini file. It is generated when the application is run, not when it is built. The compile_summary and link_summary are generated when the kernels and xclbin are built. |
@randyh62 Is |
Yes, but you must have the proper settings in the XRT.INI file. Refer to the following sections of the docs: |
Hi,
xrt.ini
u50.cfg
|
Hi andy39866821, I ran the hw_emu build just to see if it worked. I ran essentially the same commands as you, and used your u50.cfg file and your xrt.ini file contents. It worked fine and generated the xrt.run_summary file as expected. The comparison of your commands and my commends are below, though I did not see an obvious error in your commands. ANDY: g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${XILINX_XRT}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ ANDY: emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1 ANDY: v++ -c -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ../../src/u50.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo ANDY: v++ -l -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --config ../../src/u50.cfg ./vadd.xo -o vadd.xclbin ANDY: setenv XCL_EMULATION_MODE hw_emu INFO: Found Xilinx Platform /Vitis-Tutorials/Getting_Started/Vitis/example/u50> ll hw_emu/ |
9750b9b Merge pull request Xilinx#142 from mlechtan/next daf8329 Fix for CR-1110410, fix for FFT's heap size allocation and dyn stage handling. 349cfeb Fix for CR-1112154 ce41c3c Merge pull request Xilinx#5 from FaaSApps/next b0b3c30 fix_cr-1111508 (Xilinx#141) 100d912 Merge pull request Xilinx#138 from ariea/next 1ced2ce Merge branch 'next' into next d29cb2b add common resources for HTML reports 2ae6069 add an new case to support gui=true (Xilinx#129) 57c06d3 Merge pull request Xilinx#134 from mlechtan/merge_pr128 892db94 Merge branch 'next' into merge_pr128 543190d Fix for architecture reporting method for FIRs 01287ea Add dsplib QoR harvesting scripts (Xilinx#128) e277243 update makefiles using updated makefile-generator 2e65fca Merge pull request Xilinx#135 from FaaSApps/crvo3463 614cc5c makefile update uut_out_dir to static dir 0338e3f Revert last commit 34caed6 change uut_out_dir to static dir a283a95 Merge pull request Xilinx#4 from FaaSApps/next 9a0aca4 get_stats fix 68e2713 FIR Decimate Sym fix to verify crvo3463 2d43b15 update get_stats 6048e65 Fix for architecture reporting. dac2eb5 Enabling cfloat ptsize=16 to be cascaded f0419e8 Merge branch 'next' into next 4b2a6d5 update files from create dsplib script cdb178f Merge pull request Xilinx#132 from mlechtan/next b76cd67 Merge pull request Xilinx#133 from dbee/next e39f73b update with new param 7911add makefile updates 603ba07 min theory update 5e026a5 dds updates with streams and cleanup d84957a add safeguard to get_stats.tcl 8f00a8d remove batch_status.tcl 613e5dc Removing kernel compiler options: -Xchess=main:noodle.optim.olbb=20 -Xchess=main:backend.mist2.pnll="off" 2a754e0 Fix for CR-1110144 and ADL-696 f36ddc0 Merge pull request #1 from FaaSApps/next fb08c65 change exit method from diff.tcl to diff_exit.tcl 768dbc1 add license info b63051e add license info and update makefiles 900b68d remove redundant files 8cbd2dd remove redundant batch_status.tcl script 5153c04 add batch_status directory 3b9c9c7 commit auto-generated files from create_dsplib_zip 4d1741b Merge branch 'next' of https://gitenterprise.xilinx.com/ariea/xf_dsp into next ee4ec16 Merge branch 'next' of https://gitenterprise.xilinx.com/ariea/xf_dsp into next ad18675 makefile licenses 446247c Merge pull request Xilinx#3 from FaaSApps/next e63e0e4 fix revert 67af8a6 add license info 5f1ab0d Merge pull request #2 from FaaSApps/next c336f9b jenkinsfile fix 5 7b97d92 jenkinsfile fix 4 0cfe02e jenkinsfile fix 3 f68be8d jenkinsfile fix 2 ff3b449 fix jenkinsfile 1 d861796 fix jenkinsfile upstream dependency 162a51e Merge branch 'FaaSApps-next' into next 3dbdc16 Merge branch 'next' of https://gitenterprise.xilinx.com/FaaSApps/xf_dsp into FaaSApps-next b52830f modify jenkinsfile 76e0dd0 init commit fdaff02 init commit Co-authored-by: sdausr <sdausr@xilinx.com>
2079b9b Ethash SC prototype (Xilinx#150) c08ada1 merge tutorial (Xilinx#157) 04302db Merge pull request Xilinx#155 from changg/fix_issues f792a67 revert the change 98ccdea test 8fa693a fix security issues f60f3c8 Update Makefile (Xilinx#152) 9612886 Fix cr 1114888 1114873 (Xilinx#151) e622384 update rc4 benchmark case, reduce to 1 kernel (Xilinx#149) 8b43251 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 (Xilinx#145) 3d86755 Fix cr 1114880 1114888 (Xilinx#146) 49d5003 Merge pull request Xilinx#144 from liyuanz/replace_cflags 43651c8 replace cflags with clflags ee65b70 Add open file failure guard and mode for read-only (Xilinx#143) a05e213 Merge pull request Xilinx#141 from liyuanz/replace_blacklist 9095130 replace whiltelist/blacklist to allowlist/blocklist fb7dfd6 Merge pull request Xilinx#137 from leol/fix-CR 4454482 Merge pull request Xilinx#138 from liyuanz/next ded8552 add mem for mem limit case 80dddf9 Fix for L1 CBC SC benchmarks host build issue dd68b83 Clang format crc32c_sc.cpp with 3.9.0 version 443fa59 Merge pull request Xilinx#132 from liyuanz/next 34bc727 Merge pull request Xilinx#134 from liyuanz/replace_targets be250a9 update targes 3e28567 update e0cbc3d Refine crc32c to improve the performance of the resdu line (Xilinx#133) 884b4f9 update c790abe update 0256aac update 61cb658 update Makefile and utils.mk 359c5b6 Clang format crc32c_sc.cpp for both 3.9.0 and 8.0.0 (Xilinx#131) 92cf068 SC L3 design of CRC32C (Xilinx#123) c00352b update Makefile for Vitis Flow testcase (Xilinx#128) 33c3c23 remove ssl linkage from library,json (Xilinx#127) c67da48 Merge pull request Xilinx#126 from changg/metadata 080686b draft metadata files e3efd4d add aws support (Xilinx#124) 87f65b0 change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <sdausr@xilinx.com>
0dcda94 Merge pull request Xilinx#144 from tuol/cr_1140424 a76d87e Merge pull request Xilinx#145 from tuol/cr_1140420 cd2dbfd make two benchmark case disable, due to similiar issue with their corresponding cases in tests 35211e8 lower build frequency 331c32b Merge pull request Xilinx#142 from liyuanz/next 28b07ab update mk 9861fbd Merge pull request Xilinx#141 from tuol/cr_1137645 3cee823 add missing header of vector and future e01e471 Merge pull request Xilinx#140 from tuol/cr_1135038 aeb6da3 fix error in description.json 6f9dea0 Merge pull request Xilinx#137 from yuanqian/update_doc_next_portal d2fb2df Merge pull request Xilinx#138 from liyuanz/add_mem 2aa1d70 Merge pull request Xilinx#139 from liyuanz/add_mem 390ad14 add mem and time 474e03e update ca904f2 add mem 66ec334 update doc in next branch for portal ab09c33 Merge pull request Xilinx#136 from liyuanz/next 3e33b54 update makefile 5fbdc9c Merge pull request Xilinx#134 from changg/22.2_mks a477498 fix u280 0b9d86c 22.2 mk update 2e27386 change 2022.1_stable_latest to 2022.2_stable_latest Co-authored-by: sdausr <sdausr@xilinx.com>
Part5 mentions
.run_summary
file. However, after successful build of the kernel with Vitis 2020.2 there is no file with.run_summary
extension. What program is responsible for generating this file, and when exactly (at which step) this file should be created?The text was updated successfully, but these errors were encountered: