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How to package SD card? #114
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vmayoral
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Mar 17, 2022
9ba8ba0 Cleanup 1028 (Xilinx#119) 715ca77 update doc (Xilinx#118) bd2a926 Issue#111, solve timing issue, apply jacobian, reduce latency. (Xilinx#114) Co-authored-by: sdausr <sdausr@xilinx.com>
vmayoral
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1505cb9 Merge pull request Xilinx#136 from yuxiangz/token d2c3d1b fixed coding doesn't match 8df3436 doc standardization b30f97a Merge pull request Xilinx#133 from yunleiz/master 7e36c4c [host] add a file.yuv.h for resize and lepton to parser the .yuv file 2fe4329 Merge pull request Xilinx#131 from yuxiangz/token d008b09 clang format for test_decoder.cpp 404c317 fixed csynth f958425 standard coding style c7d7baa clean datas 9c26abb add order_token to master 862dd06 create master branch from next branch d249f26 Merge pull request Xilinx#121 from yunleiz/fnext a26acef [doc] refine 3e05abb Merge pull request Xilinx#119 from yunleiz/fnext c53aa56 [doc] fix pik benchamark a71c690 Merge pull request Xilinx#116 from yunleiz/fnext d431bea [doc] refine benchmark d2bcd0b [doc] update benchmark da16312 Merge pull request Xilinx#115 from liyuanz/next 8d9b470 replace -lpthread to -pthread 47bf96b Merge pull request Xilinx#114 from yunleiz/fnext bd75311 [CR]CR-1112145, update json and makefile Co-authored-by: sdausr <sdausr@xilinx.com>
vt-lib-support
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f7d1abc Merge pull request #122 from tuol/disable_2_case ae62691 disable 2 case due to U250 platform change 3af143e Merge pull request #118 from tuol/fix_cr_1122542 3e7f919 temporally disable L3/tests/mlp, due to U250 platform change 1728d13 update opts.cfg 98d3f3f Merge pull request #117 from yuanqian/next 8639708 remove email from Jenkinsfile:https://jira.xilinx.com/browse/CR-1124831 18a7458 Merge pull request #116 from changg/wa_u280_201920 86e28ef WA for xilinx_u280_xdma_201920_3 07abe54 Merge pull request #114 from liyuanz/replace_cflags 7cb157c replace cflags with clflags 0196ded Merge pull request #113 from changg/cov_fix fc100b4 cov fix b201f43 cov fix 14067e6 Merge pull request #110 from liyuanz/next bbe42e9 fix bug 257677d Merge pull request #109 from changg/pr_108 79db50c fix makefiles 984a71c update Makefile and utils daf9820 Merge pull request #106 from liyuanz/replace_blacklist 28fe2ed replace whiltelist/blacklist to allowlist/blocklist 981b5a2 Merge pull request #105 from changg/pr_104 2f45a63 add time for hw_build a21b8db add time 7256e35 add time 5f2c36a Merge pull request #102 from changg/add_extraflags acce305 fix utils.mk 74536af fix utils.mk 3c0647e Merge pull request #101 from liyuanz/next fc26744 increase mem 7a1b220 Merge pull request #99 from changg/fix_mks 055c521 fix typ 44ff7b9 fix utils.mk 4050d17 Merge pull request #98 from liyuanz/replace_targets b0157d6 update targes e41fc60 Merge pull request #96 from changg/metadata f6d1e26 draft metadata 0bbb982 change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <sdausr@xilinx.com>
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1b75f16 Merge pull request #117 from liyuanz/add_m cfc460f update 1b1fd0c Merge pull request #116 from tuol/cr_1138695 990951d remove connectivity from opts.cfg fcff114 Merge pull request #112 from liyuanz/next 3c583c5 Merge branch 'next' into next d148b7e Merge pull request #115 from tuol/1135042_2 517ab80 fix description.json 875ee0b Merge pull request #114 from tuol/cr_1135042_1 66a513b fix description.json 818c768 Merge pull request #113 from tuol/cr_1138695 0dd07e2 add missing app.bin 246611d update mk be55cf9 Merge pull request #111 from tuol/cr_1138321_1 0a3d580 fix --nk option in connectivity setup c48114c Merge pull request #110 from tuol/cr_1138321 35c48bc fix makefile, description.json and connectivity setup of cscmv and cscmvSingleHBM 651be1e Merge pull request #109 from tuol/cr_1135042 e4becb4 remove un-allowed properties from description.json 370087d Merge pull request #107 from yuanqian/update_doc_next_portal b4d95f0 Merge pull request #108 from liyuanz/add_mem 5fb26ce add mem 90fb7b8 update 24b1d5e add memory f454c44 update doc in next branch for portal 0ea11e4 Merge pull request #105 from yuanqian/update_hls_pragma 3491287 Merge pull request #106 from liyuanz/next 4c5d9a3 update f81ca5a update hls pragma ab89f67 change 2022.1_stable_latest to 2022.2_stable_latest 20d34e9 Merge pull request #103 from tuol/fix_conf_py 5b45226 update conf.py eb29003 Update Jenkinsfile Co-authored-by: sdausr <sdausr@xilinx.com>
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After I enter
make sd_card TARGET=hw DEVICE=/home/yt/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/xilinx_zcu102_base/platform_repo/xilinx_zcu102_base_202020_1/export/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm HOST_ARCH=x86
I got following message:
Successfully wrote (26549795 bytes) to the output file: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/build_dir.hw.xilinx_zcu102_base_202020_1/krnl_warptransform.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [23:50:47] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1585.496 ; gain = 0.000 ; free physical = 11793 ; free virtual = 23353
INFO: [v++ 60-1443] [23:50:47] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/build_dir.hw.xilinx_zcu102_base_202020_1/krnl_warptransform.xclbin.info --input /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/build_dir.hw.xilinx_zcu102_base_202020_1/krnl_warptransform.xclbin
INFO: [v++ 60-1454] Run Directory: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/_x_temp.hw.xilinx_zcu102_base_202020_1/link/run_link
INFO: [v++ 60-1441] [23:50:47] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1585.496 ; gain = 0.000 ; free physical = 11790 ; free virtual = 23351
INFO: [v++ 60-1443] [23:50:47] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line:
INFO: [v++ 60-1454] Run Directory: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/_x_temp.hw.xilinx_zcu102_base_202020_1/link/run_link
INFO: [v++ 60-1441] [23:50:47] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1585.496 ; gain = 0.000 ; free physical = 11790 ; free virtual = 23351
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/reports/_build.hw.xilinx_zcu102_base_202020_1/krnl_warptransform/link/system_estimate_krnl_warptransform.xtxt
INFO: [v++ 60-2397] Platform default or user specified output type sd_card detected but is not a supported output for v++ --link. Use the v++ --package option instead to create SD card output.
INFO: [v++ 60-586] Created build_dir.hw.xilinx_zcu102_base_202020_1/krnl_warptransform.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/reports/_build.hw.xilinx_zcu102_base_202020_1/krnl_warptransform/link/v++_link_krnl_warptransform_guidance.html
Timing Report: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/reports/_build.hw.xilinx_zcu102_base_202020_1/krnl_warptransform/link/imp/impl_1_xilinx_zcu102_base_wrapper_timing_summary_routed.rpt
Vivado Log: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/_x_temp.hw.xilinx_zcu102_base_202020_1/logs/link/vivado.log
Steps Log File: /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/_x_temp.hw.xilinx_zcu102_base_202020_1/logs/link/link.steps.log
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/yt/Vitis_Libraries-master/vision/L2/examples/warptransform/build_dir.hw.xilinx_zcu102_base_202020_1/krnl_warptransform.xclbin.link_summary
INFO: [v++ 60-791] Total elapsed time: 0h 21m 12s
INFO: [v++ 60-1653] Closing dispatch client.
emconfigutil --platform /home/yt/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/xilinx_zcu102_base/platform_repo/xilinx_zcu102_base_202020_1/export/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm --od build_dir.hw.xilinx_zcu102_base_202020_1
****** configutil v2020.2 (64-bit)
**** SW Build (by xbuild) on 2020-11-18-05:13:29
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
INFO: [ConfigUtil 60-895] Target platform: /home/yt/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/xilinx_zcu102_base/platform_repo/xilinx_zcu102_base_202020_1/export/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm
INFO: [ConfigUtil 60-1578] This platform contains Xilinx Shell Archive '/home/yt/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/xilinx_zcu102_base/platform_repo/xilinx_zcu102_base_202020_1/export/xilinx_zcu102_base_202020_1/hw/xilinx_zcu102_base_202020_1.xsa'
INFO: [ConfigUtil 60-1032]
emulation configuration file
emconfig.json
is created in build_dir.hw.xilinx_zcu102_base_202020_1 directoryIt seems like build .xclbin successfully, but fail to create SD image.
Then I took a look on Makefile, and following looks like the command to package SD card
PACKAGE_FILES include $(EMBEDDED_EXEC_SCRIPT),which is run_script.sh, but I couldn't find this file.
Do anyone know how to solve it or how to get this file?
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