Runtime-First FPGA Interchange Routing Contest @ FPGA’24

ℹ️ NOTE:	This contest has now concluded! Link to the results and details from our top 5 teams.

Please report all issues using the GitHub Issues feature, and ask questions under Discussions.

All content in this repository, except for third-party software otherwise attributed (e.g. Gradle, benchmark assets, etc.) is licensed under:

SPDX-License-Identifier: MIT

Utilities:

net_printer -- inspect the routing of nets in a Physical Netlist.
DcpToFPGAIF -- process a DCP into FPGAIF Logical and Physical Netlists for use with this contest.
wirelength_analyzer -- compute a critical-path wirelength for a routed FPGAIF Physical Netlist.
DiffPhysNetlist -- display any illegal differences (placement, intra-site routing, global/static inter-site routing) between two FPGAIF Physical Netlists.

Name		Name	Last commit message	Last commit date
Latest commit History 96 Commits
.github/workflows		.github/workflows
RapidWright @ 425d89e		RapidWright @ 425d89e
alpha_submission		alpha_submission
docs		docs
final_submission		final_submission
fpga-interchange-schema @ c985b46		fpga-interchange-schema @ c985b46
gradle/wrapper		gradle/wrapper
net_printer		net_printer
networkx-proof-of-concept-router		networkx-proof-of-concept-router
scoring_formula		scoring_formula
src/com/xilinx/fpga24_routing_contest		src/com/xilinx/fpga24_routing_contest
wirelength_analyzer		wirelength_analyzer
.gitignore		.gitignore
.gitmodules		.gitmodules
LICENSE.MIT		LICENSE.MIT
Makefile		Makefile
README.md		README.md
build.gradle		build.gradle
compute-score.py		compute-score.py
gradlew		gradlew
requirements.txt		requirements.txt
settings.gradle		settings.gradle

Xilinx/fpga24_routing_contest