Releases: Xilinx/fpga24_routing_contest
Releases · Xilinx/fpga24_routing_contest
v1.8
To run against the "hidden" benchmark set used for final evaluation:
make BENCHMARKS="rapidwright_picoblazearray corundum_100g koios_clstm_like_large titan23_orig_gsm_x6 corescore_900 koios_dla_like_large_v2 finn_mobilenetv1 ispd16_fpga03 mlcad_d181 boom_soc_v2 corescore_1200 ispd16_example2_v2 titan23_orig_dart_x4 corescore_1700" BENCHMARKS_URL="https://github.com/Xilinx/fpga24_routing_contest/releases/latest/download/benchmarks-evaluation.tar.gz"
What's Changed
- Post final submission cleanup by @eddieh-xlnx in #81
- Announcing the top 5 teams, with overview slide and video by @eddieh-xlnx in #87
- Announce exact results by @eddieh-xlnx in #88
- Add details of benchmarks used for final evaluation by @eddieh-xlnx in #89
Full Changelog: v1.7.1...v1.8
v1.7.1
Release used for evaluating final submissions.
What's Changed
- [Makefile] Track user-cpu time (not used for scoring) by @eddieh-xlnx in #78
- Disable network access for {run-,test-} container recipes by @eddieh-xlnx in #79
- [Actions] Move to latest actions by @eddieh-xlnx in #80
Full Changelog: v1.7...v1.7.1
v1.7
What's Changed
- [Makefile] Improve Apptainer isolation by @eddieh-xlnx in #72
- [WirelengthAnalyzer] Add support for CMACE4 by @eddieh-xlnx in #73
- [WirelengthAnalyzer] Support IMUX_CMT pip and FIFO18E2 cell by @eddieh-xlnx in #75
- Final submission updates by @eddieh-xlnx in #74
- [PartialRouterPhysNetlist] Increase maxIterations to 150 by @eddieh-xlnx in #77
- Do not restrict CheckPhysNetlist to 6G outside of Actions by @eddieh-xlnx in #76
Full Changelog: v1.6...v1.7
v1.6
What's Changed
- [CheckPhysNetlist] Verify placement & static/clock routing unchanged by @eddieh-xlnx in #64
- [Docs] Fix boom_med_pb & corundum_25g OOC=false by @eddieh-xlnx in #68
- Add DiffPhysNetlist utility by @eddieh-xlnx in #66
- [CheckPhysNetlist] Fix NullPointerException by @eddieh-xlnx in #67
- Cleanup Makefile by @eddieh-xlnx in #70
- Add logicnets_jscl and finn_radioml, with fixes by @eddieh-xlnx in #69
- [RWRoute] Add --lutRoutethru option (disabled by default) by @eddieh-xlnx in #71
Full Changelog: v1.5.1...v1.6
v1.5.1
What's Changed
- [NXRoute] Eliminate route conflicts with pre-routed nets by @eddieh-xlnx in #55
- [GHA] Fix net_printer workflow to have correct parent net names by @eddieh-xlnx in #57
- Makefile fixes by @eddieh-xlnx in #58
- [WirelengthAnalyzer] Support U-turns in Laguna tiles by @eddieh-xlnx in #56
- [WirelengthAnalyzer] Add support for IBUFDS_GTE4 cells by @eddieh-xlnx in #62
- [RapidWright] Pull in benchmark fixes by @eddieh-xlnx in #63
Full Changelog: v1.5...v1.5.1
v1.5
What's Changed
- Fix wirelength_analyzer when terminating at a comb cell (e.g. LUT) by @eddieh-xlnx in #50
- [NXRoute] Allow routethru PIPs for non-CLE/RCLK tiles by @eddieh-xlnx in #51
- [wirelength_analyzer] Add support for DIFFINBUF by @eddieh-xlnx in #52
- [RapidWright] Pull in PhysNetlistWriter + RWRoute fixes by @eddieh-xlnx in #53
Full Changelog: v1.4...v1.5
v1.4
What's Changed
- Update RapidWright submodule to latest by @eddieh-xlnx in #45
- Update requirements.txt to use pre-release pycapnp by @eddieh-xlnx in #46
- Update RapidWright with many RWRoute optimizations by @eddieh-xlnx in #47
- Alpha submission by @zakn-amd in #48
- Fix stubs in corundum_25g by @eddieh-xlnx in #49
Full Changelog: v1.3...v1.4
v1.3
What's Changed
- Fix wirelength_analyzer regex warnings by @eddieh-xlnx in #32
- PIP Clarifications by @zakn-amd in #33
- wirelength_analyzer to check PIP tile before assigning zero WL by @eddieh-xlnx in #34
- [Actions] Downgrade to Java 17 by @eddieh-xlnx in #41
- [WirelengthAnalyzer] Add new connectivity rules by @zakn-amd in #40
- Update RapidWright submodule by @eddieh-xlnx in #42
- Add 6 new benchmarks by @zakn-amd in #43
Full Changelog: v1.2...v1.3
v1.2
What's Changed
- Q/A Serial Equivalency by @clavin-xlnx in #22
- [Doc] Add "Inspecting Solutions Using Vivado" by @eddieh-xlnx in #20
- Extend registration deadline to November 20 by @eddieh-xlnx in #23
- make xcvu3p.device to use -Xmx14g by @eddieh-xlnx in #27
- Wirelength Analyzer by @zakn-amd in #25
- Add important note on Vivado ML Enterprise Edition by @eddieh-xlnx in #29
- [Actions] Update to Java 21, Python 3.12; cleanup requirements by @eddieh-xlnx in #30
- Add detailed scoring criteria by @zakn-amd in #31
Full Changelog: v1.1.1...v1.2
v1.1.1
This release contains the fixed benchmarks.tar.gz
courtesy of #21.
What's Changed
- Fix DcpToFPGAIF to add alternate SitePinInst to net by @eddieh-xlnx in #21
Full Changelog: v1.1...v1.1.1