dtbindings: vphy: Add support for Versal

Add support for Versal HDMI GT controller PHY. This adds two new
required parameters for Rx and Tx FRL reference clock.

The compatible string is also updated for Versal.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>

Documentation/devicetree/bindings/xlnx,vphy.txt

@@ -2,6 +2,7 @@ Xilinx VPHY (Staging)
 
 The Xilinx Video PHY is a high-level video-specific wrapper around
 different versions of the GT PHY. Its driver is phy/phy-xilinx-vphy.c
+This now supports HDMI on Versal too.
 
 It offers the PHY driver interface as well as higher-level video
 specific support functions.
@@ -12,6 +13,7 @@ Its current users are Xilinx HDMI RX/TX SS.
 
 Required Properties:
  - compatible: Should be "xlnx,vid-phy-controller-2.2".
+   For Versal it should be "xlnx,hdmi-gt-controller-1.0".
  - reg: Base address and size of the IP core.
  - interrupts: Interrupt number.
  - interrupts-parent: phandle for interrupt controller.
@@ -21,15 +23,15 @@ Required Properties:
           NOTE: Auto generated DT is providing all the clock names and handles
           reuired by the IP.
           NOTE: The identification string, "vid_phy_axi4lite_aclk", is always
-          required.
+          required in non Versal mode. In Versal, the string is "axi4lite_aclk".
           NOTE: The identification string "dru-clk" is always required if
           NI DRU (nidru parameter) is selected for phy. This needs to be
           explicitly added in the list of clock-names and its phandle in clocks
           as its derived by external clock.
 
  - xlnx,input-pixels-per-clock: IP configuration for samples/clk (1, 2, 4)
          Note: Only 2 is supported at this time
- - xlnx,nidru: flag to indicate if DRU is present
+ - xlnx,nidru: flag to indicate if DRU is present.
  - xlnx,nidru-refclk-sel: DRU clock selector
  - xlnx,rx-no-of-channels: Required Rx channels for registered protocol
  - xlnx,rx-pll-selection: Rx pll selector
@@ -47,6 +49,8 @@ Required Properties:
  - xlnx,use-gt-ch4-hdmi: Enables the usage of 4th TX GT channel.
                       (Default value is 0.
                       If selected in GUI, then value will be 1)
+ - xlnx,rx-frl-refclk-sel: Reference clock for Rx in FRL mode in Versal only
+ - xlnx,tx-frl-refclk-sel: Reference clock for Tx in FRL mode in Versal only
 
  - lane<n>: (port (child) nodes)
 	lane0:
@@ -104,3 +108,47 @@ sharing VPHYs, and are therefore subject to change.)
 			#phy-cells = <4>;
 		};
 	};
+
+==Example for Versal==
+
+	hdmi_gt_controller_1: hdmi_gt_controller@a4080000 {
+			clock-names = "gt_refclk1_odiv2", "sb_aclk", "axi4lite_aclk", "apb_clk", "dru-clk";
+			clocks = <&misc_clk_0>, <&versal_clk 65>, <&versal_clk 65>, <&versal_clk 65>, <&si570_2>;
+			compatible = "xlnx,hdmi-gt-controller-1.0";
+			interrupt-names = "irq";
+			interrupt-parent = <&gic>;
+			interrupts = <0 84 4>;
+			reg = <0x0 0xa4080000 0x0 0x10000>;
+			xlnx,err-irq-en = <0>;
+			xlnx,hdmi-fast-switch = <0>;
+			xlnx,input-pixels-per-clock = <2>;
+			xlnx,nidru = <1>;
+			xlnx,nidru-refclk-sel = <2>;
+			xlnx,rx-frl-refclk-sel = <2>;
+			xlnx,rx-no-of-channels = <4>;
+			xlnx,rx-pll-selection = <8>;
+			xlnx,rx-protocol = <3>;
+			xlnx,rx-refclk-sel = <0>;
+			xlnx,transceiver-type = <7>;
+			xlnx,transceiver-width = <2>;
+			xlnx,tx-buffer-bypass = <1>;
+			xlnx,tx-frl-refclk-sel = <2>;
+			xlnx,tx-no-of-channels = <4>;
+			xlnx,tx-pll-selection = <7>;
+			xlnx,tx-protocol = <1>;
+			xlnx,tx-refclk-sel = <1>;
+			xlnx,use-gt-ch4-hdmi = <1>;
+			vphy_lane0: vphy_lane@0 {
+				#phy-cells = <4>;
+			};
+			vphy_lane1: vphy_lane@1 {
+				#phy-cells = <4>;
+			};
+			vphy_lane2: vphy_lane@2 {
+				#phy-cells = <4>;
+			};
+			vphy_lane3: vphy_lane@3 {
+				#phy-cells = <4>;
+			};
+		};
+