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Refactor AIRLowering pass with mlir typeConverter #644

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merged 2 commits into from
Jul 3, 2024
Merged

Refactor AIRLowering pass with mlir typeConverter #644

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64c81b6
Refactor air-to-std lowering for scf.for, par, yield and reduce ops u…
erwei-xilinx Jul 2, 2024
61d582a
Add -air-dma-to-channel to experimental passes
erwei-xilinx Jul 2, 2024
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186 changes: 45 additions & 141 deletions mlir/lib/Conversion/AIRLoweringPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -571,6 +571,10 @@ class AIRChannelPutToAIRRtConversion

// Get src and dst memref types
auto getOps = getTheOtherChannelOpThroughSymbol(op);
if (getOps.empty()) {
op->emitOpError("failed to find the 'put' side of this air.channel");
return failure();
}
auto getOp = getOps[0];

Operation *airrtOp =
Expand Down Expand Up @@ -616,6 +620,10 @@ class AIRChannelGetToAIRRtConversion

// Get src and dst memref types
auto putOps = getTheOtherChannelOpThroughSymbol(op);
if (putOps.empty()) {
op->emitOpError("failed to find the 'get' side of this air.channel");
return failure();
}
auto putOp = putOps[0];

Operation *airrtOp =
Expand Down Expand Up @@ -727,16 +735,7 @@ class ScfYieldOpConversion : public OpConversionPattern<scf::YieldOp> {
LogicalResult
matchAndRewrite(scf::YieldOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
SmallVector<Value, 8> operands{adaptor.getOperands()};
SmallVector<Type, 2> retTys;
for (auto t : op->getResultTypes()) {
if (llvm::isa<air::AsyncTokenType>(t)) {
retTys.push_back(airrt::EventType::get(op->getContext()));
} else {
retTys.push_back(t);
}
}
rewriter.replaceOpWithNewOp<scf::YieldOp>(op, retTys, operands);
rewriter.replaceOpWithNewOp<scf::YieldOp>(op, adaptor.getOperands());
return success();
}
};
Expand Down Expand Up @@ -793,7 +792,6 @@ class ScfReduceReturnOpConversion
LogicalResult
matchAndRewrite(scf::ReduceReturnOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
SmallVector<Value, 8> operands{adaptor.getOperands()};
SmallVector<Type, 2> retTys;
for (auto t : op->getResultTypes()) {
if (llvm::isa<air::AsyncTokenType>(t)) {
Expand All @@ -802,7 +800,8 @@ class ScfReduceReturnOpConversion
retTys.push_back(t);
}
}
rewriter.replaceOpWithNewOp<scf::ReduceReturnOp>(op, retTys, operands);
rewriter.replaceOpWithNewOp<scf::ReduceReturnOp>(op, retTys,
adaptor.getOperands());
return success();
}
};
Expand Down Expand Up @@ -851,58 +850,19 @@ class ScfForOpConversion : public OpConversionPattern<scf::ForOp> {
LogicalResult
matchAndRewrite(scf::ForOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
auto newOp = rewriter.replaceOpWithNewOp<scf::ForOp>(
op, adaptor.getLowerBound(), adaptor.getUpperBound(), adaptor.getStep(),
adaptor.getInitArgs());
auto body = op.getBody();
auto newBody = newOp.getBody();
rewriter.setInsertionPointToStart(newBody);

IRMapping remap;
for (int i = 0, e = body->getNumArguments(); i < e; i++) {
auto arg = body->getArgument(i);
auto newArg = newBody->getArgument(i);
if (isa<airrt::EventType>(newArg.getType())) {
auto cast = rewriter.create<UnrealizedConversionCastOp>(
op->getLoc(), arg.getType(), newArg);
remap.map(arg, cast.getResult(0));
} else {
remap.map(arg, newArg);
}
}
for (auto &o : body->getOperations()) {
if (isa<scf::YieldOp>(o)) {
SmallVector<Value> opers;
for (int i = 0, e = o.getNumOperands(); i < e; i++) {
auto oper = remap.lookupOrDefault(o.getOperand(i));
if (llvm::isa<air::AsyncTokenType>(oper.getType())) {
auto ty = airrt::EventType::get(o.getContext());
auto cast = rewriter.create<UnrealizedConversionCastOp>(
op->getLoc(), ty, oper);
opers.push_back(cast->getResult(0));
} else {
opers.push_back(oper);
}
}
rewriter.create<scf::YieldOp>(o.getLoc(), opers);
} else {
rewriter.clone(o, remap);
}
}
scf::ForOp newOp =
dyn_cast<scf::ForOp>(rewriter.cloneWithoutRegions(*op.getOperation()));
rewriter.inlineRegionBefore(op.getRegion(), newOp.getRegion(),
newOp.getRegion().end());

// Set operands and update block argument and result types.
newOp->setOperands(adaptor.getOperands());
if (failed(rewriter.convertRegionTypes(&newOp.getRegion(), *typeConverter)))
return failure();
for (auto result : newOp.getResults())
result.setType(typeConverter->convertType(result.getType()));

// Cast result types back to air.asyncTokenType using
// UnrealizedConversionCastOp.
rewriter.setInsertionPointAfter(newOp);
SmallVector<Value> newResults;
for (auto res : newOp->getResults()) {
if (llvm::isa<airrt::EventType>(res.getType())) {
auto ty = air::AsyncTokenType::get(op->getContext());
auto cast =
rewriter.create<UnrealizedConversionCastOp>(op->getLoc(), ty, res);
newResults.push_back(cast.getResult(0));
} else
newResults.push_back(res);
}
rewriter.replaceOp(op, newOp.getResults());
return success();
}
};
Expand All @@ -914,76 +874,19 @@ class ScfParOpConversion : public OpConversionPattern<scf::ParallelOp> {
LogicalResult
matchAndRewrite(scf::ParallelOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
SmallVector<Value> newInitVals;
for (auto initVal : adaptor.getInitVals()) {
if (llvm::isa<air::AsyncTokenType>(initVal.getType())) {
auto cast = rewriter.create<UnrealizedConversionCastOp>(
op->getLoc(), airrt::EventType::get(op->getContext()), initVal);
newInitVals.push_back(cast.getResult(0));
} else
newInitVals.push_back(initVal);
}

auto hasNElements = [](Block *block, unsigned N) {
unsigned counter = 0;
for (auto &o : block->getOperations()) {
if (o.mightHaveTrait<OpTrait::IsTerminator>())
continue;
if (isa<air::WaitAllOp>(o))
continue;
counter++;
}
return counter == N;
};

Operation *newOp = nullptr;
auto body = op.getBody();
if (hasNElements(body, 0))
// If empty scf.parallel body, then replace the scf.parallel with
// airrt.wait_all (no-op).
newOp = rewriter.create<airrt::WaitAllOp>(
op->getLoc(), airrt::EventType::get(op->getContext()), newInitVals);
else {
auto newParOp = rewriter.create<scf::ParallelOp>(
op->getLoc(), adaptor.getLowerBound(), adaptor.getUpperBound(),
adaptor.getStep(), newInitVals);
newOp = newParOp.getOperation();
auto newBody = newParOp.getBody();
rewriter.setInsertionPointToStart(newBody);
IRMapping remap;
for (int i = 0, e = body->getNumArguments(); i < e; i++) {
auto arg = body->getArgument(i);
auto newArg = newBody->getArgument(i);
if (isa<airrt::EventType>(newArg.getType())) {
auto cast = rewriter.create<UnrealizedConversionCastOp>(
op->getLoc(), arg.getType(), newArg);
remap.map(arg, cast.getResult(0));
} else {
remap.map(arg, newArg);
}
}
for (int i = 0, e = op.getNumReductions(); i < e; i++)
replaceAllUsesInRegionWith(op.getInitVals()[i],
newParOp.getInitVals()[i],
newParOp.getRegion());
for (auto &o : body->getOperations())
rewriter.clone(o, remap);
}
scf::ParallelOp newOp = dyn_cast<scf::ParallelOp>(
rewriter.cloneWithoutRegions(*op.getOperation()));
rewriter.inlineRegionBefore(op.getRegion(), newOp.getRegion(),
newOp.getRegion().end());

// Set operands and update block argument and result types.
newOp->setOperands(adaptor.getOperands());
if (failed(rewriter.convertRegionTypes(&newOp.getRegion(), *typeConverter)))
return failure();
for (auto result : newOp.getResults())
result.setType(typeConverter->convertType(result.getType()));

// Cast result types back to air.asyncTokenType using
// UnrealizedConversionCastOp.
rewriter.setInsertionPointAfter(newOp);
SmallVector<Value> newResults;
for (auto res : newOp->getResults()) {
if (llvm::isa<airrt::EventType>(res.getType())) {
auto ty = air::AsyncTokenType::get(op->getContext());
auto cast =
rewriter.create<UnrealizedConversionCastOp>(op->getLoc(), ty, res);
newResults.push_back(cast.getResult(0));
} else
newResults.push_back(res);
}
rewriter.replaceOp(op, newResults);
rewriter.replaceOp(op, newOp.getResults());
return success();
}
};
Expand Down Expand Up @@ -1150,21 +1053,22 @@ class AIRLoweringPass : public air::impl::AIRLoweringBase<AIRLoweringPass> {
}
return true;
});
target.addIllegalOp<air::WaitAllOp>();
target.addLegalOp<UnrealizedConversionCastOp>();

air_patterns.add<
ScfYieldOpConversion, ScfIfOpConversion, ScfParOpConversion,
ScfReduceReturnOpConversion, ScfReduceOpConversion, ScfForOpConversion,
L2AllocToAIRRtConversion, L2DeallocToAIRRtConversion,
AIRLaunchConversion, AIRSegmentConversion, AIRHerdConversion>(context);
air_patterns
.add<L2AllocToAIRRtConversion, L2DeallocToAIRRtConversion,
AIRLaunchConversion, AIRSegmentConversion, AIRHerdConversion>(
context);

populateFunctionOpInterfaceTypeConversionPattern<func::FuncOp>(air_patterns,
converter);

air_patterns
.add<AIRDmaMemcpyNdToAIRRtConversion, AIRChannelPutToAIRRtConversion,
AIRChannelGetToAIRRtConversion, AIRWaitAllToAIRRtConversion>(
converter, context);
.add<ScfYieldOpConversion, ScfIfOpConversion, ScfForOpConversion,
ScfParOpConversion, ScfReduceReturnOpConversion,
ScfReduceOpConversion, AIRDmaMemcpyNdToAIRRtConversion,
AIRWaitAllToAIRRtConversion, AIRChannelPutToAIRRtConversion,
AIRChannelGetToAIRRtConversion>(converter, context);

if (failed(
applyPartialConversion(module, target, std::move(air_patterns)))) {
Expand Down
1 change: 1 addition & 0 deletions python/air/compiler/aircc/main.py
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@
"air-dependency",
"air-dependency-schedule-opt",
"air-specialize-dma-broadcast",
"air-dma-to-channel",
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doesn't it already contain air-dma-to-channel? Do you just need a different order?
Starting about line 375:

        pass_pipeline = ",".join(
            [
                "air-insert-launch-and-segment-around-herd",
                "func.func(air-lower-herd-parallel)",
            ]
            + (
                EXPERIMENTAL_PASSES
                if "npu" in opts.device and opts.experimental_passes
                else []
            )
            + (["air-dma-to-channel"] if "npu" in opts.device else [])
            + [
                "canonicalize",
                "cse",
                "air-specialize-channel-wrap-and-stride",
                "func.func(air-renumber-dma)",
                "func.func(convert-linalg-to-loops)",
                air_place_pass,
            ]

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Yes we need air-dma-to-channel to produce us with air.channel ops before the following passes:

    "func.func(air-loop-fusion)",
    "air-label-scf-for-to-ping-pong",
    "air-ping-pong-transform{keep-memref-dealloc=true}",
    "air-isolate-async-dma-loop-nests",

Those passes are for BD optimizations, and they only work on air.channels, because air.dma_memcpy_nd doesn't have explicit handles for BDs.

"canonicalize",
"cse",
"air-dependency-canonicalize",
Expand Down
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