Fix Travis build

.travis.yml

@@ -1,6 +1,6 @@
 sudo: required
 dist: trusty
-script: make ICEBOX=/usr/share/fpga-icestorm/chipdb test
+script: make test
 language: cpp
 addons:
   apt:
@@ -15,7 +15,11 @@ addons:
 before_install:
   - sudo add-apt-repository -y ppa:saltmakrell/ppa
   - sudo apt-get -y update
-  - sudo apt-get -y install yosys fpga-icestorm
+  - sudo apt-get -y install yosys
+  - git clone https://github.com/cliffordwolf/icestorm /tmp/icestorm
+  - pushd /tmp/icestorm
+  - make -j2 && sudo make install
+  - popd
 os: linux
 compiler:
   - gcc

tests/combinatorial/generate.py

@@ -31,7 +31,7 @@ def random_term(variables):
     return term
 
 for idx in range(25):
-    with file('temp/uut_%05d.v' % idx, 'w') as f:
+    with open('temp/uut_%05d.v' % idx, 'w') as f:
         with redirect_stdout(f):
             pins = 96
 
@@ -88,15 +88,15 @@ def random_term(variables):
                 print('  assign o%d = %s;' % (i, term))
 
             print('endmodule')
-    with file('temp/uut_%05d.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             print('rename uut_%05d gate' % idx)
             print('read_verilog temp/uut_%05d.v' % idx)
             print('rename uut_%05d gold' % idx)
             print('hierarchy; proc;;')
             print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
             print('sat -verify-no-timeout -timeout 20 -prove trigger 0 -show-inputs -show-outputs miter')
-    with file('temp/uut_%05d_pp.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d_pp.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             print('rename uut_%05d gate' % idx)
             print('read_verilog temp/uut_%05d.v' % idx)

tests/fsm/generate.py

@@ -45,7 +45,7 @@ def random_expr(variables):
     raise AssertionError
 
 for idx in range(25):
-    with file('temp/uut_%05d.v' % idx, 'w') as f:
+    with open('temp/uut_%05d.v' % idx, 'w') as f:
         with redirect_stdout(f):
             rst2 = random.choice([False, True])
             if rst2:
@@ -125,15 +125,15 @@ def random_expr(variables):
             print('    end')
             print('  end')
             print('endmodule')
-    with file('temp/uut_%05d.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             print('rename uut_%05d gate' % idx)
             print('read_verilog temp/uut_%05d.v' % idx)
             print('rename uut_%05d gold' % idx)
             print('hierarchy; proc;;')
             print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
             print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
-    with file('temp/uut_%05d_pp.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d_pp.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             print('rename uut_%05d gate' % idx)
             print('read_verilog temp/uut_%05d.v' % idx)

tests/simple/run-test.sh

@@ -48,7 +48,4 @@ for d in $devices; do
         icepack $d/$pll.txt $d/$pll.bin
     done
 
-    $arachne_pnr -d $d tri.blif -o $d/tri.txt
-    shasum $d/tri.txt >> txt.sum
-    icepack $d/tri.txt $d/tri.bin
 done