Fix initialization of "irq" in verilog testbench

Signed-off-by: Clifford Wolf <clifford@clifford.at>
YosysHQ · Sep 22, 2019 · 3f9b504 · 3f9b504
1 parent 881f928
commit 3f9b504
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/testbench.v b/testbench.v
@@ -75,7 +75,7 @@ module picorv32_wrapper #(
 	output [35:0] trace_data
 );
 	wire tests_passed;
-	reg [31:0] irq;
+	reg [31:0] irq = 0;
 
 	reg [15:0] count_cycle = 0;
 	always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;

diff --git a/testbench_wb.v b/testbench_wb.v
@@ -65,7 +65,7 @@ module picorv32_wrapper #(
 	output [35:0] trace_data
 );
 	wire tests_passed;
-	reg [31:0] irq;
+	reg [31:0] irq = 0;
 	wire mem_instr;
 
 	reg [15:0] count_cycle = 0;