Added vhdl "make install"

vhdl/Makefile

@@ -2,6 +2,7 @@ CXX = $(shell yosys-config --cxx)
 CXXFLAGS = $(shell yosys-config --cxxflags)
 LDFLAGS = $(shell yosys-config --ldflags)
 LDLIBS = $(shell yosys-config --ldlibs)
+PLUGINS_DIR = $(shell yosys-config --datdir)/plugins
 
 OBJS = vhdl_parser.tab.o vhdl_lexer.o vhdl_frontend.o preproc.o
 
@@ -22,6 +23,11 @@ vhdl_lexer.cc: vhdl_lexer.l def.h vhdl_parser.tab.h
 test:
 	cd test; ./runtests
 
+.PHONY: install
+install: vhdl.so
+	mkdir -p $(PLUGINS_DIR)
+	cp vhdl.so $(PLUGINS_DIR)/vhdl.so
+
 clean:
 	rm -f *.d *.o vhdl.so vhdl_lexer.cc vhdl_parser.output vhdl_parser.tab.cc vhdl_parser.tab.h
 

vhdl/README

@@ -1,2 +1,7 @@
-VHDL front-end plugin, based on commit 97edbf90b8433b285534a372dcfc74b68f58a671 
-of https://github.com/SebKuzminsky/yosys/tree/vhdl-frontend.
+
+VHDL front-end plugin, upstream for this plugin:
+https://github.com/SebKuzminsky/yosys-plugins/tree/master/vhdl
+
+Based on vhdl2vl. See https://github.com/ldoolitt/vhd2vl/tree/master/examples
+for more example VHDL files.
+

vhdl/test/runtests

@@ -16,7 +16,7 @@ for V in *.vhd; do
     BASENAME=$(basename $V .vhd)
     echo test: ${BASENAME}
     AST=${BASENAME}.ast
-    yosys -m /home/seb/fpga/yosys-plugins/vhdl/vhdl.so -p "read_vhdl -dump_ast1 $V" > ${AST}
+    yosys -m ../vhdl.so -p "read_vhdl -dump_ast1 $V" > ${AST}
     cleanup_ast ${AST}
     if ! diff -u ${AST}-expected ${AST}; then
         echo "error: ${AST} does not match expected"