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Unused signal not output in trace for cover mode #1441
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Two Verilog sources, one,
test_case_good.v
ports out a signalunf
, while the other,test_case_bad.v
does not. Otherwise, the logic is the same. Running a cover pass on these files passes, but looking at the traces, the vcd file fortest_case_good.v
shows theunf
signal, while fortest_case_bad.v
does not containunf
at all! This is inconvenient, especially when signals are buried two or three modules deep and are unused, but are needed for debugging.test_case.zip
Here is the diff between the sources where right=good, left=bad:
See also: nmigen original report
Steps to reproduce the issue
test_case_bad
intest_case.sby
.sby -f test_case.sby
.test_case_cover/engine_0/trace0.vcd
.unf
is not present.test_case_good
.unf
is present.Expected behavior
The
unf
signal is present in the trace provided viatest_case_bad
.Actual behavior
The
unf
signal is not present in the trace provided viatest_case_bad
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