$finish statement in always blocks produce errors

[Dolu1990]

Steps to reproduce the issue

yosysFinishIssue.zip

just do a make in the decompressed archive.

Actual behavior

Toplevel.v:17: Warning: System task `$display' outside initial block is unsupported.
Toplevel.v:18: ERROR: System task `$finish' outside initial block is unsupported.
makefile:2: recipe for target 'compile' failed

Expected behavior

Yosys should probably process the $finish statement as a warning, not as an error/failure, as it does for the $display statement.

I tested that code on Quartus, Vivado, Diamond synthesis, none of them process $finish statement as error / failure.

Using the $finish statement in synthetisable RTL always blocks seem to me the only way to write simulation runtime assertions with regular verilog.

[whitequark]

Using the $finish statement in synthetisable RTL always blocks seem to me the only way to write simulation runtime assertions with regular verilog.

You can use `ifdef SYNTHESIS, which every 1364.1-2002 compliant tool must accept:

[Dolu1990]

@whitequark
Thanks for the info, didn't know the SYNTHESIS stuff was part of the spec.
So for me that's fine, it fix my issue.

Still, should it be keept open because of the $display $finish inequality of treatment and the interpolability it produce with other synthesis tools ?
Not saying the other tools do things right, just that it is how it is.

[rodrigomelo9]

I tested that code on Quartus, Vivado, Diamond synthesis, none of them process $finish statement as error / failure.

The same (ignored) in case of ISE. I recently submitted a similar issue (#1801, I didn't saw this issue before, sorry).

I think that the ERROR is ok, to abort if a condition is not accomplished, but the message mustn't be unsupported, because the behaviour is the same that inside of an initial block (nested under a if).