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Rename flip-flops with custom suffix #3195
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After applying the patch you can do |
Is this option give user have cell/FF in netlist with same RTL ? Preferred format <rtl_cell_name>_reg : This helps in quick gate-level, ECO and LEC and Is there is example scripts to show which place this command need to applied . |
Is is custom script integrated into yosys main branch ? I see tool gives with below error while integrating this patch |
We don't want to provide anything that looks like a standard because we don't have any way to guarantee consistent naming of these cells in situations more complex than a simple assignment to a FF (e.g., if there are any bit selections, slices, concatenations). There will always be cases where the names would not match what another tool will do, or even what a different combination of yosys passes will create. Therefore no one should build any script relying on those names, and if they are only read by a human then it should not make a difference if it says |
@nakengelhardt |
@dineshannayya The rename command is part of Yosys. Its help text can be found here: https://yosyshq.net/yosys/cmd_rename.html |
@nakengelhardt It does make a difference, especially if you're using Verilog as backend. The |
@bfg86 I am looking for way to keep cell instance name matching as in RTL. Not sure how rename rule helps here when user will no access to RTL name for a give cell instance. |
@dineshannayya The rename -wire renames the selection based on the name of the wire that the cell is driving. Guessing a bit here: do you have a tech cell instantiated in your RTL, and are you looking for something like dont_touch or size_only in Design Compiler? (guessing since you mentioned a NAND gate in your example) |
Note that this message comes from the tcl builtin
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@dineshannayya cell instance names should always be preserved. The whole issue here is about cells that are inferred from behavioral logic, so they do not have any name in the RTL at all. Most of the FFs in a design come from a pattern like this:
In this pattern the only thing that has a name is the signal d, which is actually the output wire driven by the D port of the inferred $dff cell. The $dff cell is anonymous since it was not instantiated manually, so it gets a private name (starting in If you are actually seeing an explicit instance name not being preserved, can you give more context in the other issue? |
I am facing the same issue of flipflops renaming after synthesis. Could you tell how to retain(get) names of the filpflops after synthesis same as RTL. sky130_fd_sc_hd_dfrtp_2 _14258 ( |
@dineshannayya respected sir, |
I'd like to have meaningful names for flip-flops (makes it easier for debugging). So I tried
rename -wire t:$*DFF*
before dfflibmap.
This gave names with the flop type as a suffix, for example
\ready$_DFFE_PP1P_
I made a patch so its possible to have a custom suffix when running rename -wire. Wondering if anyone else are interested in this patch.
This would make it easier to debug a netlist, and also do name-matching vs RTL in third-party tools (like LEC).
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