Rename flip-flops with custom suffix

[bfg86]

I'd like to have meaningful names for flip-flops (makes it easier for debugging). So I tried
rename -wire t:$*DFF*
before dfflibmap.
This gave names with the flop type as a suffix, for example
\ready$_DFFE_PP1P_
I made a patch so its possible to have a custom suffix when running rename -wire. Wondering if anyone else are interested in this patch.
This would make it easier to debug a netlist, and also do name-matching vs RTL in third-party tools (like LEC).

[bfg86]

After applying the patch you can do
rename -wire -suffix _reg t:$*DFF*
and the same register would be called
ready_reg
in the netlist.

[dineshannayya]

Is this option give user have cell/FF in netlist with same RTL ?
My issue Yosys is: Yosys netlist generation does not follow the industry standard naming conversion in
preserve cell instance name
Example: Currently in netlist cells instance name with number like 06637
sky130_fd_sc_hd__nand2_2 06637 ( .A(01599), .B(01620), .Y(01621));

Preferred format <rtl_cell_name>_reg : This helps in quick gate-level, ECO and LEC and
STA debug.

Is there is example scripts to show which place this command need to applied .

[dineshannayya]

Is is custom script integrated into yosys main branch ?

I see tool gives with below error while integrating this patch
ERROR: TCL interpreter returned an error: wrong # args: should be "rename oldName newName"

[nakengelhardt]

We don't want to provide anything that looks like a standard because we don't have any way to guarantee consistent naming of these cells in situations more complex than a simple assignment to a FF (e.g., if there are any bit selections, slices, concatenations). There will always be cases where the names would not match what another tool will do, or even what a different combination of yosys passes will create. Therefore no one should build any script relying on those names, and if they are only read by a human then it should not make a difference if it says <wirename>_reg or <wirename>$dff.

[dineshannayya]

@nakengelhardt
Current yosys cell naming scheme (instance name with number) is a critical drawback compare to commercial graded tools.
Netlist with cell instance with matching with source RTL name is critical function to debug the LEC failure, STA analysis and Gate level simulation and debug.

[bfg86]

@dineshannayya The rename command is part of Yosys. Its help text can be found here: https://yosyshq.net/yosys/cmd_rename.html
The patch provides the -suffix option, to provide other suffix than _$<cell type>. If you want to use the patch, you can check out yosys from https://github.com/bfg86/yosys.git, change branch to bfg86/rename, and build yosys as normal.

[bfg86]

@nakengelhardt It does make a difference, especially if you're using Verilog as backend. The $ character is illegal in Verilog, so all names with $ are escaped. This makes it hard to read, and as you point out hard to write scripts for.
The patch doesn't change any default behavior, but provides an option to add whatever prefix you'd like.

[dineshannayya]

@bfg86 I am looking for way to keep cell instance name matching as in RTL. Not sure how rename rule helps here when user will no access to RTL name for a give cell instance.

[bfg86]

@dineshannayya The rename -wire renames the selection based on the name of the wire that the cell is driving.

Guessing a bit here: do you have a tech cell instantiated in your RTL, and are you looking for something like dont_touch or size_only in Design Compiler? (guessing since you mentioned a NAND gate in your example)

[jix]

ERROR: TCL interpreter returned an error: wrong # args: should be "rename oldName newName"

Note that this message comes from the tcl builtin rename not the yosys rename command. Errors from yosys commands will not be prefixed by TCL interpreter returned an error. How to invoke the yosys rename command from tcl is mentioned in yosys -h tcl:

Yosys commands 'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames' in order to avoid a name collision with the built in commands.

[nakengelhardt]

@dineshannayya cell instance names should always be preserved. The whole issue here is about cells that are inferred from behavioral logic, so they do not have any name in the RTL at all. Most of the FFs in a design come from a pattern like this:

module dff(input clk, rst, q, output reg d);
always @ ( posedge clk ) begin
	if (rst) d <= 1'b0;
	else d <= q;
end
endmodule

In this pattern the only thing that has a name is the signal d, which is actually the output wire driven by the D port of the inferred $dff cell. The $dff cell is anonymous since it was not instantiated manually, so it gets a private name (starting in $) which the tool will not try particularly to preserve. With rename -wire, the cell would be given a public name (starting in \) derived from the output wire name d, in this case \d$dff.

If you are actually seeing an explicit instance name not being preserved, can you give more context in the other issue?

[prajnaputhran17]

I am facing the same issue of flipflops renaming after synthesis. Could you tell how to retain(get) names of the filpflops after synthesis same as RTL.

sky130_fd_sc_hd_dfrtp_2 _14258 (
.CLK(CLK),
.D(00157),
.Q(mv_output[20]),
.RESET_B(RST_N)
);

[Vinayakamk]

Reference

@dineshannayya respected sir,
we faced the same issue of what u faced about registers naming,could u tell us how did u fixed.