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The design includes 64 shifter_cell_a submodules with each 6 inputs and 2 outputs, a lot of those inputs and outputs connected together. In each case only one of the multiple possible names is available in the debug_items map. A very visible example is the Reload input, which are all connected to the Reload register of the shifter_video_async top module, and ends up appearing only as "sharray[0].c0 Reload" and nowhere else.
Expected Behavior
I would have expected to have 17 names on the same signal, including "Reload" and "sharray[0..15].c0..3 Reload". Same for all the Din/Dout etc.
Actual Behavior
Right now every unique signal can only have one name, chosen semi-randomly between its aliases.
The text was updated successfully, but these errors were encountered:
Please include the complete steps to reproduce the issue, including a Yosys script and a link to a specific version of input (not a link to a branch that may change at any time).
The signals are removed by the explicit invocation of clean -purge in your Yosys script, as documented:
opt_clean [options] [selection]
This pass identifies wires and cells that are unused and removes them. Other
passes often remove cells but leave the wires in the design or reconnect the
wires but leave the old cells in the design. This pass can be used to clean up
after the passes that do the actual work.
This pass only operates on completely selected modules without processes.
-purge
also remove internal nets if they have a public name
(the documentation is a bit confusing, but that's what it means: remove unused nets even if they have a public name, which would otherwise be kept for use of cxxrtl)
Version
Yosys 0.25+3 (git sha1 f2c6894, clang 14.0.6 -fPIC -Os)
On which OS did this happen?
Linux
Reproduction Steps
Trying to use cxxrtl on https://github.com/MiSTer-devel/AtariST_MiSTer/blob/master/rtl/gstmcu/shifter_video_async.v
The design includes 64 shifter_cell_a submodules with each 6 inputs and 2 outputs, a lot of those inputs and outputs connected together. In each case only one of the multiple possible names is available in the debug_items map. A very visible example is the Reload input, which are all connected to the Reload register of the shifter_video_async top module, and ends up appearing only as "sharray[0].c0 Reload" and nowhere else.
Expected Behavior
I would have expected to have 17 names on the same signal, including "Reload" and "sharray[0..15].c0..3 Reload". Same for all the Din/Dout etc.
Actual Behavior
Right now every unique signal can only have one name, chosen semi-randomly between its aliases.
The text was updated successfully, but these errors were encountered: