Error IDELAYCTRL missing for IODELAYs when using Yosys + Vivado with basic LiteX SoC #652
Comments
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Just confirming that this occurs with the latest Yosys ( Going to try with the latest Vivado. |
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Just confirming that this also fails with latest Vivado (tried with |
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I built a version of this SoC without the SPI Flash or DDR and ended up with a You can find the output of this minimal SoC at https://github.com/mithro/litex-buildenv-arty-yosys-xilinx/tree/min |
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Might need something like https://www.xilinx.com/support/answers/68753.html |
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The issue seems to be that the IDELAYCTRL IDELAYCTRL(
.REFCLK(clk200_clk),
.RST(ic_reset)
);But the output |
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It seems by adding; And then adding a (* KEEP = "TRUE" *)
IDELAYCTRL IDELAYCTRL(
.REFCLK(clk200_clk),
.RST(ic_reset)
);Allows Vivado to generate a bitstream. I have pushed the latest working code to the repository here. |
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Should the |
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Yep. However, Regarding this script: You definitiely want to run
Idk. Maybe. But if so then other modules should as well. I'm not going to add a module-level (Just to clarify: You would of course not set it automatically on instances, which I think is what your wording implies. You'd just set it once on the module in |
Steps to reproduce the issue
You will need the latest Yosys with #650 included and Vivado with WebPack license.
Then clone this temporary repository, then try a build.
git clone https://github.com/mithro/litex-buildenv-arty-yosys-xilinx.git cd litex-buildenv-arty-yosys-xilinx ./build_top.shI have also committed the output that I have received. I'm using Vivado 2017.3 and Yosys
0.7+663 (git sha1 dc77ed1e)with the patch in pull request #650. (When I get a chance I'll use latest Vivado and Yosys.)Expected behavior
Produces a working bitstream for this design (as using Vivado's inbuilt synthesis for this design does).
You can compare the behaviour to a build which only uses Vivado at https://github.com/timvideos/HDMI2USB-firmware-prebuilt/tree/master/archive/master/v0.0.4-356-ga1093ac/arty/base/lm32/gateware
Actual behavior
When trying to use Yosys for the synthesis stage as part of a Vivado flow for an Artix 7 that uses IODELAY objects, the build fails with;
The working Vivado flow looks like the following;
create_project -force -name top -part xc7a35t-csg324-1 add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_logic_op.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_logic_op.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_shifter.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_shifter.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_multiplier.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_multiplier.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dp_ram.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dp_ram.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dcache.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dcache.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_debug.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_debug.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_itlb.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_itlb.v}] add_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dtlb.v} set_property library work [get_files {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dtlb.v}] add_files {top.v} set_property library work [get_files {top.v}] read_xdc top.xdc synth_design -top top -part xc7a35t-csg324-1 -include_dirs {/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/cores/cpu/lm32/verilog/config} report_timing_summary -file top_timing_synth.rpt report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt report_utilization -file top_utilization_synth.rpt opt_design place_design report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt report_utilization -file top_utilization_place.rpt report_io -file top_io.rpt report_control_sets -verbose -file top_control_sets.rpt report_clock_utilization -file top_clock_utilization.rpt route_design write_checkpoint -force top_route.dcp report_route_status -file top_route_status.rpt report_drc -file top_drc.rpt report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt report_power -file top_power.rpt set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] write_bitstream -force top.bit write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin quitFor
yosysthe flow I'm using is;create_project -force -name top -part xc7a35t-csg324-1 read_xdc top.xdc read_edif top.edif link_design -top top -part xc7a35t-csg324-1 report_timing_summary -file top_timing_synth.rpt report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt report_utilization -file top_utilization_synth.rpt opt_design place_design report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt report_utilization -file top_utilization_place.rpt report_io -file top_io.rpt report_control_sets -verbose -file top_control_sets.rpt report_clock_utilization -file top_clock_utilization.rpt route_design phys_opt_design report_timing_summary -no_header -no_detailed_paths write_checkpoint -force top_route.dcp report_route_status -file top_route_status.rpt report_drc -file top_drc.rpt report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt report_power -file top_power.rpt set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] write_bitstream -force top.bit write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin quitCould the issue could be related to failure to apply the following constraints?
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