util: fix cpt upgrader for rvv changes in PR gem5#83

  * Solves issue gem5#106 by updating the cpts with the necessary vector
    registers.

Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585

util/cpt_upgraders/riscv-vext.py

@@ -0,0 +1,65 @@
+def upgrader(cpt):
+    """
+    Update the checkpoint to support initial RVV implemtation.
+    The updater is taking the following steps.
+
+    1) Set vector registers/element to occupy 1280 bytes (40regs * 32bytes)
+    2) Clear vector_predicate and matrix registers
+    3) Add RVV misc registers in the checkpoint
+    """
+
+    for sec in cpt.sections():
+        import re
+
+        # Search for all XC sections
+        if re.search(".*processor.*\.core.*\.xc.*", sec):
+
+            # Updating RVV vector registers (dummy values)
+            # Assuming VLEN = 256 bits (32 bytes)
+            mr = cpt.get(sec, "regs.vector").split()
+            if len(mr) <= 8:
+                cpt.set(sec, "regs.vector", " ".join("0" for i in range(1280)))
+
+            # Updating RVV vector element (dummy values)
+            mr = cpt.get(sec, "regs.vector_element").split()
+            if len(mr) <= 16:
+                cpt.set(
+                    sec,
+                    "regs.vector_element",
+                    " ".join("0" for i in range(1280)),
+                )
+
+            # Updating RVV vector predicate (dummy values)
+            cpt.set(sec, "regs.vector_predicate", "")
+
+            # Updating RVV matrix (dummy values)
+            cpt.set(sec, "regs.matrix", "")
+
+        # Search for all ISA sections
+        if re.search(".*processor.*\.core.*\.isa$", sec):
+
+            # Updating RVV misc registers (dummy values)
+            mr = cpt.get(sec, "miscRegFile").split()
+            if len(mr) == 164:
+                print(
+                    "MISCREG_* RVV registers already seem " "to be inserted."
+                )
+            else:
+                # Add dummy value for MISCREG_VSTART
+                mr.insert(121, 0)
+                # Add dummy value for MISCREG_VXSAT
+                mr.insert(121, 0)
+                # Add dummy value for MISCREG_VXRM
+                mr.insert(121, 0)
+                # Add dummy value for MISCREG_VCSR
+                mr.insert(121, 0)
+                # Add dummy value for MISCREG_VL
+                mr.insert(121, 0)
+                # Add dummy value for MISCREG_VTYPE
+                mr.insert(121, 0)
+                # Add dummy value for MISCREG_VLENB
+                mr.insert(121, 0)
+                cpt.set(sec, "miscRegFile", " ".join(str(x) for x in mr))
+
+
+legacy_version = 17