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"util/cpt_upgrader.py" not updating RISC-V checkpoints from v23.0.0.1 to changes in #83 #106
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BobbyRBruce
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util
Utilities for gem5. Typically found in "util"
arch-riscv
The RISC-V ISA
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Jul 20, 2023
aarmejach
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Jul 24, 2023
* Solves issue gem5#106 by updating the cpts with the necessary vector registers. Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585
aarmejach
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Jul 28, 2023
* Solves issue gem5#106 by updating the cpts with the necessary vector registers. Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585 util: clear vector_element field Change-Id: I6c9ec4e71f66722b26de030fa139cd626bdb24dc
aarmejach
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Aug 4, 2023
* Solves issue gem5#106 by updating the cpts with the necessary vector registers. Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585 util: clear vector_element field Change-Id: I6c9ec4e71f66722b26de030fa139cd626bdb24dc
powerjg
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Aug 4, 2023
alvaromorenomv
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Aug 9, 2023
* Solves issue gem5#106 by updating the cpts with the necessary vector registers. Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585 util: clear vector_element field Change-Id: I6c9ec4e71f66722b26de030fa139cd626bdb24dc
@BobbyRBruce can we close this? |
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To reproduce:
The following output is returned:
Processing file checkpoint/m5.cpt.... has tags arm-miscreg-teehbr arm-ccregs arm-gem5-gic-ext dvfs-perflevel x86-add-tlb ide-dma-abort remove-arm-cpsr-mode-miscreg etherswitch armv8 register-files ruby-block-size-bytes mempool-to-seworkload process-fdmap-rename cpu-pid globals-to-root smt-interrupts memory-per-range mempool-sections isa-is-simobject arm-sysreg-mapping-ns arm-contextidr-el2 multiple-event-queues arm-hdlcd-upgrade arm-sve arm-gicv2-banked-regs ...nothing to do
I have only proven this fault when working with #83 for updating a checkpoint from v23.0.0.1 to that necessary for the PR. The limitation of "util/cpt_upgrader.py" may exist elsewhere.
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