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Pinned

  1. An Agile Chisel-Based SoC Design Framework

    Scala 146 115

  2. Forked from riscv-boom/riscv-boom

    BOOM: Berkeley Out-of-Order Machine

    Scala

  3. Forked from firesim/firesim

    FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation of RISC-V Systems (Rocket Chip, BOOM) in the Cloud

    Python 1

  4. Forked from firesim/firechip

    Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

    C

  5. Forked from firesim/icenet

    Network components (NIC, Switch) for FireBox

    Scala

  6. Forked from ccelio/coremarkpro-util-make-riscv

    The utility files to port CoreMark-Pro to RISC-V.

    Makefile

1,202 contributions in the last year

Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Mon Wed Fri

Contribution activity

December 2019

Created a pull request in ucb-bar/chipyard that received 4 comments

Control Core Example

Example MultiCore configuration with a small "control" core attached on the side (i.e. a PMU). This was requested by @jwright6323 and @alonamid.

+44 −2 4 comments

Created an issue in firesim/firesim that received 2 comments

Show `replace_rtl` output

When running replace RTL it would be nice to have the Chisel/FIRRTL output go to stdout. Therefore, if there is an error you can immediately see it…

2 comments

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