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University of California at Berkeley
- Berkeley, California
- abejgonzalez.github.io
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ucb-bar/chipyard Public
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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firesim Public
Forked from firesim/firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation of RISC-V Systems (Rocket Chip, BOOM) in the Cloud
Python 1
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firechip Public
Forked from firesim/firechip
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
C
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coremarkpro-util-make-riscv Public
Forked from ccelio/coremarkpro-util-make-riscv
The utility files to port CoreMark-Pro to RISC-V.
Makefile
835 contributions in the last year
Contribution activity
May 2022
Created 4 commits in 1 repository
Reviewed 10 pull requests in 3 repositories
firesim/firesim
6 pull requests
- VSCode Integration for Scala Development
- Constitute the local-fpga branch by merging main + vitis-integration
- Support A Resource-Minimizing strategy ("AREA") for AWS-FPGA
- [DO NOT MERGE] ("Where to Run") Support running on different run farm hosts
- XDC-Driven Memory Hints for Xilinx FPGAs
- Provide AWS creds when cleaning up after a failed manager initialization