Updated link to Anthony's L3 page

acjf3 · Mar 21, 2019 · 4dbe2fd · 4dbe2fd
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 L3 MIPS
 =======
 
-A **MIPS ISA simulator** implemented in [L3](http://www.cl.cam.ac.uk/~acjf3/l3/ "L3: An ISA Specification Language").
+A **MIPS ISA simulator** implemented in [L3](https://acjf3.github.io/l3/index.html).
 The simulator also supports [CHERI](http://www.chericpu.org "Capability Hardware Enhanced RISC Instructions (CHERI) ") capability extensions.
 
 Getting started