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Allows passing Verilog parameters at synthesis time
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adumont committed Jul 10, 2018
1 parent a9bc676 commit 49c44b773ed24270388aa9cdddc6b99d45d94300
Showing with 45 additions and 9 deletions.
  1. +3 −1 .gitignore
  2. +15 −1 verilog/Design.mk
  3. +12 −5 verilog/Makefile
  4. +11 −2 verilog/top.v
  5. +4 −0 verilog/top_wrapper.m4
@@ -6,4 +6,6 @@
*.bin
*.ivl
*.pnr
*.log
*.log
top_wrapper.v
build.config
@@ -37,8 +37,22 @@ else ifeq ($(MODULE), hrmcpu)

endif

IVERILOG_MACRO=
M4_OPTIONS=
AUXFILES=

ifdef PROGRAM
M4_OPTIONS += -D_PROGRAM_=$(PROGRAM)
DEPS := top_wrapper.v $(filter-out top_wrapper.v,$(DEPS))
AUXFILES += $(PROGRAM)
endif

ifdef ROMFILE
M4_OPTIONS += -D_ROMFILE_=$(ROMFILE)
DEPS := top_wrapper.v $(filter-out top_wrapper.v,$(DEPS))
AUXFILES += $(ROMFILE)
endif

IVERILOG_MACRO=
ifdef PROGRAM
IVERILOG_MACRO:=$(IVERILOG_MACRO) -DPROGRAM=\"$(PROGRAM)\"
endif
@@ -29,10 +29,10 @@ gtkwave: $(MODULE).v $(DEPS) $(MODULE)_tb.v $(MODULE)_tb.vcd

gtkwave $(MODULE)_tb.vcd $(MODULE)_tb.gtkw &

$(MODULE).bin: $(MODULE).pcf $(MODULE).v $(DEPS)
$(MODULE).bin: $(MODULE).pcf $(MODULE).v $(DEPS) $(AUXFILES) build.config

yosys -p "synth_ice40 -top $(MODULE) -blif $(MODULE).blif $(YOSYSOPT)" \
-l $(MODULE).log -q $(MODULE).v $(DEPS)
-l $(MODULE).log -q $(DEPS) $(MODULE).v

arachne-pnr -d $(MEMORY) -p $(MODULE).pcf $(MODULE).blif -o $(MODULE).pnr

@@ -53,11 +53,18 @@ assets/$(MODULE)_dot.svg: $(MODULE).v $(DEPS)
[ -f $(MODULE)_dot.dot ] && rm $(MODULE)_dot.dot

upload: $(MODULE).bin

iceprog $(MODULE).bin

# We save AUXFILES names to build.config. Force a rebuild if they have changed
build.config: $(AUXFILES) .force
@echo '$(AUXFILES)' | cmp -s - $@ || echo '$(AUXFILES)' > $@

top_wrapper.v: top_wrapper.m4 build.config
m4 $(M4_OPTIONS) top_wrapper.m4 > top_wrapper.v

clean:

rm -f *.bin *.pnr *.blif *.out *.vcd *~
rm -f *.bin *.pnr *.blif *.out *.vcd *~ top_wrapper.v build.config

.PHONY: all clean json svg sim dot
.PHONY: all clean json svg bin sim dot .force

@@ -1,5 +1,7 @@
`ifndef __TOP_MODULE__
`define __TOP_MODULE__

`default_nettype none
//`include "const.vh"

// Use of `define allows override from iverilog using -Dkey=value
`ifndef PROGRAM
@@ -23,6 +25,12 @@ module top (

localparam baudsDivider=24'd104;

initial begin
// will dump parameters values in the yosys log
$display("PARAM PROGRAM: %s",`PROGRAM);
$display("PARAM ROMFILE: %s",`ROMFILE);
end

wire sw1_d; // pulse when sw pressed
wire sw1_u; // pulse when sw released
wire sw1_s; // sw state
@@ -150,4 +158,5 @@ module out2txCtl (
end
end

endmodule
endmodule
`endif // __TOP_MODULE__
@@ -0,0 +1,4 @@
changequote([,])dnl
`define PROGRAM "_PROGRAM_"
`define ROMFILE "_ROMFILE_"
`include "top.v"

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