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  1. ravenoc Public

    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

    SystemVerilog 80 22

  2. axi_dma Public

    General Purpose AXI Direct Memory Access

    SystemVerilog 13 2

  3. RISCV model for Verilator/FPGA targets

    C 30 10

  4. Benchmark for Hwacha vector accelerator of vvadd computation tweaked

    C 2

  5. Verilog 27 8

  6. SystemVerilog

625 contributions in the last year

Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Mon Wed Fri
Activity overview
Contributed to aignacio/axi_dma, aignacio/openmp_eval_arm, aignacio/ravenoc and 18 other repositories

Contribution activity

December 2022

Created 1 commit in 1 repository
1 contribution in private repositories Dec 2

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