Skip to content
View akinglw's full-sized avatar
Block or Report

Block or report akinglw

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. picorv32 picorv32 Public

    Forked from YosysHQ/picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog

  2. verilog-axi verilog-axi Public

    Forked from alexforencich/verilog-axi

    Verilog AXI components

    Verilog

  3. AXI_BFM AXI_BFM Public

    Forked from ptracton/AXI_BFM

    AXI4 BFM in Verilog

    Verilog

  4. AMBA-AXI4-Lite AMBA-AXI4-Lite Public

    Forked from somyadashora/AMBA-AXI4-Lite

    Master and Slave made using AMBA AXI4 Lite protocol.

    Stata

  5. System-Bus-Design-Verilog System-Bus-Design-Verilog Public

    Forked from Buddhimah/System-Bus-Design-Verilog

    This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification

    Verilog

  6. Implementation-of-AMBA-AXI3-protocol Implementation-of-AMBA-AXI3-protocol Public

    Forked from HunterBitos/Implementation-of-AMBA-AXI3-protocol

    Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware e…

    SystemVerilog