back.verilog, back.rtlil: map path elements to str

amaranth-lang · Apr 19, 2024 · d2b2c9b · d2b2c9b
1 parent dde8334
commit d2b2c9b
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py
@@ -1289,7 +1289,7 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
                     dir = _ir.PortDirection.Input
                 else:
                     dir = _ir.PortDirection.Output
-                ports["__".join(path)] = (value, dir)
+                ports["__".join(map(str, path))] = (value, dir)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
     fragment = _ir.Fragment.get(elaboratable, platform)

diff --git a/amaranth/back/verilog.py b/amaranth/back/verilog.py
@@ -54,7 +54,7 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
                     dir = _ir.PortDirection.Input
                 else:
                     dir = _ir.PortDirection.Output
-                ports["__".join(path)] = (value, dir)
+                ports["__".join(map(str, path))] = (value, dir)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
     fragment = _ir.Fragment.get(elaboratable, platform)