Constraint generation from platform resource with DiffPairs of type LVDS incorrect.

[lethalbit]

When helping someone out with something involving Amaranth, I noticed that the latest main does not generate proper constraints for LVDS DiffPairs, causing place and route to fail due to it wanting to bind to both signals for the buffer and not just the non-inverted end of the signal.

In this case it was using the VersaECP5Platform from amaranth-boards. Specifically that board has a differential LVDS clock as the default clock, and as it stands any design using that platform is unable to be fully placed and routed due to that.

Using the minimal blink example, the generated constraints for the LVDS signal are:

LOCATE COMP "clk100_0__p" SITE "P3";
IOBUF PORT "clk100_0__p" IO_TYPE=LVDS;
LOCATE COMP "clk100_0__n" SITE "P4";
IOBUF PORT "clk100_0__n" IO_TYPE=LVDS;

Which is not correct.

I ran a git bisect from when v0.5.0.dev0 was first tagged (597b1b8) up to HEAD from main, and it looks like commit cf53448 is the commit that caused the failure.

I've not done much more digging into the cause, but I figured y'all would like to know.

[whitequark]

We'll look into it. Thanks!

@wanda-phi