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Design & Implementation of a balanced five stage pipelined MIPS Processor ensuring improved performance using pipelining & hazard control methods Tools and Languages: Synopsys Verilog Compiler Simulator (VCS), Synopsys Design Vision, Verilog

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ameyjain/VERILOG-Five-stage-32-bit-MIPS-processor

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3 Commits
README.md
README.md
 
 
alu_ctrl.v
alu_ctrl.v
 
 
mips_alu.v
mips_alu.v
 
 
mips_controller.v
mips_controller.v
 
 
mips_cpu_top.v
mips_cpu_top.v
 
 
mips_datapath.v
mips_datapath.v
 
 
reg_file.v
reg_file.v
 
 
shifter.v
shifter.v
 
 
tb_mips.v
tb_mips.v
 
 

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VERILOG-Five-stage-32-bit-MIPS-processor

Design & Implementation of a balanced five stage pipelined MIPS Processor ensuring improved performance using pipelining & hazard control methods Tools and Languages: Synopsys Verilog Compiler Simulator (VCS), Synopsys Design Vision, Verilog

The tb_mips.v file contains testbench for running the project.

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Design & Implementation of a balanced five stage pipelined MIPS Processor ensuring improved performance using pipelining & hazard control methods Tools and Languages: Synopsys Verilog Compiler Simulator (VCS), Synopsys Design Vision, Verilog

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