Intel CPU Garage Challenge
Desigin a CPU compatible with the "hack" ISA.
For more information regarding the specification see https://www.nand2tetris.org/
4 Stage Pipe line
Treating the DataMem as "register file" due to the support of A, M, D registers-Register operations. (M - is the the Memory register)
Fetching 20 instructions per cycle - able to excecute up to 10 instruction.
The 20 insturciton is due to the "delay" of a cycle of updating the PC - This way the next 10 instruction are available Back2Back.
Option to accelerate copmutation using HW Devider.
Using modelsim (vlog & vsim commands) to simulate & test the design.
The source files (same files for FPGA) FPGA_CPUGarage/sv/*
Using Deticated files for simulation: (memory, TB, defines) source/*
Generated trackers on memory access used for debug modelsim/reference_log/* , modelsim/trk_d_mem_access.log
Reference model - Starting point - golden solution from Design original_reference/*
Open the qpf gui file: FPGA_CPUGarage/FPGA_CPUGarage.qpf
