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Updated fsbl build script for Zynq7000
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Signed-off-by: Pagadarai <Srikanth.Pagadarai@analog.com>
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@SrikanthPagadarai
SrikanthPagadarai committed Mar 31, 2023
1 parent 9d25038 commit 391d87a
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Showing 3 changed files with 53 additions and 77 deletions.
20 changes: 5 additions & 15 deletions CI/scripts/fsbl_build_zynq.tcl
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Original file line number Diff line number Diff line change
@@ -1,21 +1,12 @@


### Calling script must have system_top.hdf u-boot.elf
### Calling script must generated have system_top.bit


set cdir [pwd]
set sdk_loc $cdir/vivado_prj.sdk

### Create fsbl
hsi open_hw_design $sdk_loc/system_top.hdf
set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]
sdk setws $sdk_loc
sdk createhw -name hw_0 -hwspec $sdk_loc/system_top.hdf
sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}
configapp -app fsbl build-config release
sdk projects -build -type all

### Copy common zynq.bif file
### Copy common dependent files for ZCU102
file mkdir $cdir/boot
file copy -force $cdir/projects/common/boot/zynq.bif $cdir/boot/zynq.bif
if {$argc == 1} {
Expand All @@ -24,12 +15,11 @@ if {$argc == 1} {
file copy -force $cdir/projects/common/boot/u-boot.elf $cdir/boot/u-boot.elf
}

### Copy fsbl and system_top.bit into the output folder
file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf
file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit
### Copy system_top.bit into the output folder
file copy -force $cdir/projects/common/boot/fsbl.elf $cdir/boot/fsbl.elf
file copy -force $cdir/vivado_prj.runs/impl_1/system_top.bit $cdir/boot/system_top.bit

### Build BOOT.BIN
cd $cdir/boot
exec bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w
exit

109 changes: 47 additions & 62 deletions CI/scripts/read_ports_json.py
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Original file line number Diff line number Diff line change
Expand Up @@ -4,80 +4,65 @@
ports_json_file = 'ports.json'
with open(ports_json_file) as json_file:
ports = json.load(json_file)

tmp_key = "m_name"
for key0 in ports.keys():
m_names = dict()
for key1 in ports[key0]['ports'][0].keys():
if (key1 == "rx"):
for ii in range(0, len(ports[key0]['ports'][0][key1])):
tmp_dict = ports[key0]['ports'][0][key1][ii]
if tmp_key not in tmp_dict:
if (tmp_dict['type'].lower() == "data"):
if (tmp_dict['input'] == "true") :
if (tmp_dict['type'].lower() == "data"):
if (tmp_dict['input'] == "true"):
if tmp_key not in tmp_dict:
tmp_list = tmp_dict['name'].split("_")
last_ele = tmp_list[-1]
ip = ""
if (len(last_ele) == 2) :
ip = f"{ports[key0]['chip']} ADC Data {last_ele.upper()}"
else :
ip = f"{ports[key0]['chip']} ADC Data 0 IN"
if ip in m_names :
m_names[ip] += 1
ip = f"{ports[key0]['chip']} ADC Data {m_names[ip]} IN"
else :
m_names[ip] = 0
tmp_dict[tmp_key] = ip
elif (tmp_dict['input'] == "false"):
if tmp_key not in tmp_dict:
ip = f"IP Data 0 OUT"
if ip in m_names :
m_names[ip] += 1
tmp_dict[tmp_key] = f"IP Data {m_names[ip]} OUT"
else :
m_names[ip] = 0
tmp_dict[tmp_key] = ip

elif (tmp_dict['type'].lower() == "valid"):
if (tmp_dict['input'] == "true"):
tmp_dict[tmp_key] = f"IP Valid Rx Data IN"
elif (tmp_dict['input'] == "false"):
tmp_dict[tmp_key] = f"IP Data Valid OUT"
last_ele = tmp_list[-1]
if (len(last_ele) == 1):
res = divmod(int(last_ele), 2)
if res[1]:
i_or_q = "Q"
else:
i_or_q = "I"
tmp_dict[tmp_key] = f"{ports[key0]['chip']} ADC Data {i_or_q}{res[0]}"
elif (len(last_ele) == 2):
tmp_dict[tmp_key] = f"{ports[key0]['chip']} ADC Data {last_ele.upper()}"
elif (tmp_dict['input'] == "false"):
if tmp_key not in tmp_dict:
tmp_list = tmp_dict['name'].split("_")
last_ele = tmp_list[-1]
tmp_dict[tmp_key] = f"IP Data {last_ele.upper()} OUT"
elif (tmp_dict['type'].lower() == "valid"):
if (tmp_dict['input'] == "true"):
tmp_dict[tmp_key] = f"IP Valid Rx Data IN"
elif (tmp_dict['input'] == "false"):
tmp_dict[tmp_key] = f"IP Data Valid OUT"
ports[key0]['ports'][0][key1][ii] = tmp_dict

elif (key1 == "tx"):
for ii in range(0, len(ports[key0]['ports'][0][key1])):
tmp_dict = ports[key0]['ports'][0][key1][ii]
if tmp_key not in tmp_dict :
if (tmp_dict['type'].lower() == "data") :
if (tmp_dict['input'] == "false"):
if (tmp_dict['type'].lower() == "data"):
if (tmp_dict['input'] == "false"):
if tmp_key not in tmp_dict:
tmp_list = tmp_dict['name'].split("_")
last_ele = tmp_list[-1]
ip = ""
if (len(last_ele) == 2):
ip = f"{ports[key0]['chip']} DAC Data {last_ele.upper()}"
else:
ip = f"{ports[key0]['chip']} DAC Data 0 OUT"
if ip in m_names :
m_names[ip] += 1
ip = f"{ports[key0]['chip']} DAC Data {m_names[ip]} OUT"
else :
m_names[ip] = 0
tmp_dict[tmp_key] = ip
elif (tmp_dict['input'] == "true"):
if tmp_key not in tmp_dict:
ip = f"IP Data 0 IN"
if ip in m_names :
m_names[ip] += 1
tmp_dict[tmp_key] = f"IP Data {m_names[ip]} IN"
else :
m_names[ip] = 0
tmp_dict[tmp_key] = ip

elif (tmp_dict['type'].lower() == "valid"):
if (tmp_dict['input'] == "true"):
tmp_dict[tmp_key] = f"IP Valid Tx Data IN"
elif (tmp_dict['input'] == "false"):
tmp_dict[tmp_key] = f"IP Load Tx Data OUT"
last_ele = tmp_list[-1]
if (len(last_ele) == 1):
res = divmod(int(last_ele), 2)
if res[1]:
i_or_q = "Q"
else:
i_or_q = "I"
tmp_dict[tmp_key] = f"{ports[key0]['chip']} DAC Data {i_or_q}{res[0]}"
elif (len(last_ele) == 2):
tmp_dict[tmp_key] = f"{ports[key0]['chip']} DAC Data {last_ele.upper()}"
elif (tmp_dict['input'] == "true"):
if tmp_key not in tmp_dict:
tmp_list = tmp_dict['name'].split("_")
last_ele = tmp_list[-1]
tmp_dict[tmp_key] = f"IP Data {last_ele.upper()} IN"
elif (tmp_dict['type'].lower() == "valid"):
if (tmp_dict['input'] == "true"):
tmp_dict[tmp_key] = f"IP Valid Tx Data IN"
elif (tmp_dict['input'] == "false"):
tmp_dict[tmp_key] = f"IP Load Tx Data OUT"
ports[key0]['ports'][0][key1][ii] = tmp_dict

with open(ports_json_file, 'w') as json_file:
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1 change: 1 addition & 0 deletions test/build_design.m
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
hWC.ProjectFolder = folder;
hWC.ReferenceDesignToolVersion = vivado_version;
hWC.IgnoreToolVersionMismatch = true;
hWC.AllowUnsupportedToolVersion = true;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndIPCore = true;
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