Updated ADRV9001 designs

Signed-off-by: Pagadarai <Srikanth.Pagadarai@analog.com>
analogdevicesinc · Apr 10, 2023 · 6c101c9 · 6c101c9
1 parent 21bfd78
commit 6c101c9
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/CI/scripts/matlab_processors.tcl b/CI/scripts/matlab_processors.tcl
@@ -394,10 +394,10 @@ proc preprocess_bd {project carrier rxtx} {
             switch $carrier {                
                 zcu102 {                    
                     # Add 1 extra AXI master ports to the interconnect
+					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect]
                     set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect]
                     # Connect clock and reset
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins sys_ps8/pl_clk0]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn]
+					connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins sys_ps8/pl_clk0]
                 }                
             }
         }