ADRV9001 Clock domain crossing between Tx and Rx

- Initial commit

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

CI/scripts/build_bsp.sh

@@ -98,4 +98,7 @@ cp scripts/fixmake.sh  ../hdl/vendor/AnalogDevices/vivado/projects/scripts/fixma
 mkdir ../hdl/vendor/AnalogDevices/vivado/projects/common/boot/
 cp -r scripts/boot/* ../hdl/vendor/AnalogDevices/vivado/projects/common/boot/
 
+# Copy additional IP files
+cp -r scripts/library/* ../hdl/vendor/AnalogDevices/vivado/library/
+
 echo 'puts "Skipping"' > ../hdl/vendor/AnalogDevices/vivado/library/axi_ad9361/axi_ad9361_delay.tcl

CI/scripts/library/util_sync/sync_delay/Makefile

@@ -0,0 +1,13 @@
+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := util_delay
+
+GENERIC_DEPS += util_delay.v
+
+XILINX_DEPS += util_delay_ip.tcl
+
+include ../../scripts/library.mk

CI/scripts/library/util_sync/sync_delay/util_delay.v

@@ -0,0 +1,76 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_delay #(
+
+  parameter DATA_WIDTH = 8,
+  // the minimum valid value for DELAY_CYCLES is 1
+  parameter DELAY_CYCLES = 3
+) (
+  input                             clk,
+  input                             rstn,
+  input   [DATA_WIDTH-1:0]          din,
+  output  [DATA_WIDTH-1:0]          dout
+);
+
+  reg     [DATA_WIDTH-1:0]          dbuf[0:(DELAY_CYCLES-1)];
+
+  always @(posedge clk) begin
+    //if (rstn == 0) begin
+    if (rstn == 0) begin
+      dbuf[0] <= 0;
+    end else begin
+      dbuf[0] <= din;
+    end
+  end
+
+  generate
+  genvar i;
+    for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe
+      always @(posedge clk) begin
+        if (rstn == 0) begin
+          dbuf[i] <= 0;
+        end else begin
+          dbuf[i] <= dbuf[i-1];
+        end
+      end
+    end
+  endgenerate
+
+  assign dout = dbuf[(DELAY_CYCLES-1)];
+
+endmodule

CI/scripts/library/util_sync/sync_delay/util_delay_ip.tcl

@@ -0,0 +1,47 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
+#
+# Each core or library found in this collection may have its own licensing terms.
+# The user should keep this in in mind while exploring these cores.
+#
+# Redistribution and use in source and binary forms,
+# with or without modification of this file, are permitted under the terms of either
+#  (at the option of the user):
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory, or at:
+# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
+#
+# OR
+#
+#   2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
+# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+adi_ip_create util_delay
+adi_ip_files util_delay [list \
+  "util_delay.v" ]
+
+adi_ip_properties_lite util_delay
+
+set cc [ipx::current_core]
+
+foreach {k v} { \
+  "DELAY_CYCLES" "Delay Cycles" \
+  "DATA_WIDTH" "Data Width" \
+  } { \
+  set p [ipgui::get_guiparamspec -name $k -component $cc]
+#  ipgui::move_param -component $cc -order $i $p -parent $
+  set_property -dict [list \
+    DISPLAY_NAME $v \
+  ] $p
+  incr i
+}
+
+ipx::save_core [ipx::current_core]

CI/scripts/library/util_sync/sync_fast_to_slow/Makefile

@@ -0,0 +1,13 @@
+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := sync_fast_to_slow
+
+GENERIC_DEPS += sync_fast_to_slow.v
+
+XILINX_DEPS += sync_fast_to_slow_ip.tcl
+
+include ../../scripts/library.mk

CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow.v

@@ -0,0 +1,136 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+/*
+ * Helper module for synchronizing bit signals from one clock domain to another.
+ * It uses the standard approach of 2 FF in series.
+ * Note, that while the module allows to synchronize multiple bits at once it is
+ * only able to synchronize multi-bit signals where at max one bit changes per
+ * clock cycle (e.g. a gray counter).
+ */
+
+`timescale 1ns/100ps
+
+module sync_fast_to_slow #(
+  // Depth of the fifo
+  parameter DEPTH = 4,
+  // Number of bits to synchronize
+  parameter WIDTH = 2,
+  // Clock ratio between fast and slow clock
+  // Used to improve latency
+  // At a ratio of 4, the design slightly changes in favor of latency
+  parameter RATIO = 4
+) (
+  input [WIDTH-1:0] in_data,
+  input in_resetn,
+  input in_clk,
+
+  output reg [WIDTH-1:0] out_data,
+  input out_resetn,
+  input out_clk
+);
+
+  reg [WIDTH-1:0] fifo [DEPTH-1:0];
+
+  reg [DEPTH/2-1:0] rd_addr;
+  reg [DEPTH/2-1:0] wr_addr;
+
+  reg cdc_sync_stage0_tick;
+  reg cdc_sync_stage1_tick;
+  reg cdc_sync_stage2_tick;
+  reg cdc_sync_stage3_tick;
+
+  wire tick;
+
+  assign tick = cdc_sync_stage2_tick ^ cdc_sync_stage3_tick;
+
+  always @(posedge out_clk)
+  begin
+    if (out_resetn == 1'b0)
+      cdc_sync_stage0_tick <= 1'b0;
+    else
+      cdc_sync_stage0_tick <= ~cdc_sync_stage0_tick;
+  end
+
+  always @(posedge in_clk)
+  begin
+    if (in_resetn == 1'b0) begin
+      cdc_sync_stage1_tick <= 1'b0;
+      cdc_sync_stage2_tick <= 1'b0;
+      cdc_sync_stage3_tick <= 1'b0;
+    end else begin
+      cdc_sync_stage1_tick <= cdc_sync_stage0_tick;
+      cdc_sync_stage2_tick <= cdc_sync_stage1_tick;
+      cdc_sync_stage3_tick <= cdc_sync_stage2_tick;
+    end
+  end
+
+  generate if (RATIO < 4) begin
+    always @(posedge in_clk)
+    begin
+      if (in_resetn == 1'b0) begin
+        wr_addr <= 0;
+      end else begin
+        if ((tick == 1'b1) || (rd_addr == wr_addr)) begin
+          fifo[wr_addr] <= in_data;
+          wr_addr <= (wr_addr + 1) % DEPTH;
+        end
+      end
+    end
+  end else begin
+    always @(posedge in_clk)
+    begin
+      if (in_resetn == 1'b0) begin
+        wr_addr <= 1;
+      end else begin
+        if (tick == 1'b1) begin
+          fifo[wr_addr] <= in_data;
+          wr_addr <= (wr_addr + 1) % DEPTH;
+        end
+      end
+    end
+  end endgenerate
+
+  always @(posedge out_clk)
+  begin
+    if (out_resetn == 1'b0)
+      rd_addr <= 0;
+    else
+      if (rd_addr != wr_addr)
+        rd_addr <= (rd_addr + 1) % DEPTH;
+	out_data <= fifo[rd_addr];
+  end
+
+endmodule

CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow_ip.tcl

@@ -0,0 +1,48 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
+#
+# Each core or library found in this collection may have its own licensing terms.
+# The user should keep this in in mind while exploring these cores.
+#
+# Redistribution and use in source and binary forms,
+# with or without modification of this file, are permitted under the terms of either
+#  (at the option of the user):
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory, or at:
+# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
+#
+# OR
+#
+#   2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
+# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+adi_ip_create sync_fast_to_slow
+adi_ip_files sync_fast_to_slow [list \
+  "sync_fast_to_slow.v" ]
+
+adi_ip_properties_lite sync_fast_to_slow
+
+set cc [ipx::current_core]
+
+foreach {k v} { \
+  "DEPTH" "FIFO Depth" \
+  "WIDTH" "Data Width" \
+  "RATIO" "Fast and slow clock ratio" \
+  } { \
+  set p [ipgui::get_guiparamspec -name $k -component $cc]
+#  ipgui::move_param -component $cc -order $i $p -parent $
+  set_property -dict [list \
+    DISPLAY_NAME $v \
+  ] $p
+  incr i
+}
+
+ipx::save_core [ipx::current_core]

CI/scripts/library/util_sync/sync_slow_to_fast/Makefile

@@ -0,0 +1,13 @@
+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := sync_slow_to_fast
+
+GENERIC_DEPS += sync_slow_to_fast.v
+
+XILINX_DEPS += sync_slow_to_fast_ip.tcl
+
+include ../../scripts/library.mk