The software interrupt is pended directly via the interrupt controlle…

…r, so no need to clear Cause.IP0.
andersm · Sep 16, 2014 · bf730f5 · bf730f5
1 parent e12fd9a
commit bf730f5
Showing 1 changed file with 0 additions and 4 deletions.
diff --git a/PIC32/tn_port_pic32mx_xc32.S b/PIC32/tn_port_pic32mx_xc32.S
@@ -190,10 +190,6 @@ cs0_int_handler:
     lw      $sp, 0($t1)                 /* get new task's sp */
     sw      $t1, 0($t0)                 /* tn_curr_run_task = tn_next_task_to_run */
 
-    mfc0    $k0, $13                    /* c0_cause */
-    ins     $k0, $zero, 8, 1            /* clear IP0 */
-    mtc0    $k0, $13
-
     lui     $k0, %hi(IFS0CLR)           /* clear cs0 pending bit */
     ori     $k1, $zero, 2
     sw      $k1, %lo(IFS0CLR)($k0)