QL: tests: design3: add keep attr

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
antmicro · Apr 22, 2020 · f277733 · f277733
1 parent 17cf29f
commit f277733
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diff --git a/quicklogic/tests/quicklogic_testsuite/design3/AL4S3B_FPGA_IP.v b/quicklogic/tests/quicklogic_testsuite/design3/AL4S3B_FPGA_IP.v
@@ -416,6 +416,7 @@ outpad u_outpad_I27 ( .A( SOUT_o        ), .P( SOUT         ) );
 
 // I2S Slave (RX mode) support with DMA
 //
+(* keep *)
 i2s_slave_w_DMA              #(
 
     .ADDRWIDTH                 ( ADDRWIDTH_DMA_REG              ),

diff --git a/quicklogic/tests/quicklogic_testsuite/design3/AL4S3B_FPGA_Top.v b/quicklogic/tests/quicklogic_testsuite/design3/AL4S3B_FPGA_Top.v
@@ -193,6 +193,7 @@ gclkbuff u_gclkbuff_clock48khz ( .A(SYS_C21_ACSLIPREF_Clk_sig ) , .Z(sys_ref_clk
 
 // Example FPGA Design
 //
+(* keep *)
 AL4S3B_FPGA_IP             
 
      u_AL4S3B_FPGA_IP        (
@@ -255,6 +256,7 @@ AL4S3B_FPGA_IP
 
 // Empty Verilog model of QLAL4S3B
 //
+(* keep *)
 qlal4s3b_cell_macro              u_qlal4s3b_cell_macro
                                (
     // AHB-To-FPGA Bridge