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xtensa: add support for Espressif chips #13
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This compiles and runs, but I have yet to get ESP32 code running. I suspect that's because I don't have the boot ROM running yet, but this patchset is required to even start working on peripheral compatibility. |
Hi @xobs, thanks for submitting the PR - it would be great to add ESP32 support. We are looking at your changes and I assume we can just merge those soon; what kind of firmware are you trying to enable? Our normal approach would probably be to try to get Zephyr to run (to bump our Zephyr dashboard stats ;-) ) but I assume you may be trying to run something else, it would be good to know what to be able to collaborate on this! |
The motivation for this was actually to run a workshop at CCCamp next month, in order to introduce people to Renode. The badge uses an ESP32S3, so support for those cores would need to be merged. In terms of supporting a brand-new chip, from my work with Precursor it seems like I'd mostly be able to just add peripherals, which can be done in the context of a workshop. The tricky bit would be to get support for all of the CPU features, and I believe this patch accomplishes that. |
Currently, the ESP32S3 needs to run through the internal boot ROM in order to set up things like Windowed Mode on the CPU. I've extracted the boot ROM from a device I have on-hand, but I'm unclear whether this could be distributed as part of Renode. Even so, I think we can whack in values to various registers to get it working without the boot ROM. Regardless, I have a basic UART FIFO working, and I'm at least able to see messages with this patch. |
Nice catch! It does not break anything I can see so far. As an aside: I'm at a point now where I need to get interrupts working, because the boot ROM is waiting for the SPI block to return the flash ID and I suspect it's waiting for an interrupt. Are there any examples of Xtensa interrupt controllers? Should they be supported? The ESP32S3 has an interrupt core that muxes its 96 interrupts to the Xtensa's 32 interrupts, so I'll need to implement that before anything gets further. |
Add support for the Espressif line of chips, comprising ESP32, ESP32S2, and ESP32S3. This contains code taken from Xtensa in order to define the part-specific configurations. Signed-off-by: Sean Cross <sean@xobs.io>
I don't know about the interrupts bit, but FYI we're targeting to merge this one today. |
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Add support for the Espressif line of chips, comprising ESP32, ESP32S2, and ESP32S3.
This contains code taken from Xtensa in order to define the part-specific configurations.