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Fix stm32xx GPIO glitches from configuration bad order of operations #4589

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merged 4 commits into from
Sep 22, 2021

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davids5
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@davids5 davids5 commented Sep 21, 2021

Summary

The PR fixes stm32xx GPIO glitches from GPIO configuration with bad order of operations

When I2C was initialized the SDA and SCL lines would glitch low. The Bosch BMM150 was locking up from this.

Glitch on init Capture

The root cause on a STM32F12 was that the IO PAD was connected and driven (by the default IP block) BEFORE the IP block (I2C) was routed to the PAD via the alternate selection mux.

The fix is two fold:

  1. On a to-ALT configuration: Configure the ALT selection MUX before the IO direction is changed.
  2. On a from-ALT configuration (unconfigure): Configure the ALT selection MUX after the IO direction is changed.

The Glitch on the unconfigure

On_deinit

On a Conner case testing HW stack checking this change exposed a timing related bug in the SDIO/SDMMC driver that was the result of redundant GPIO configurations dropping interrupts. This is fixed in 18d7204

Impact

STM32, STM32F7, STM32H7

Testing

Bench tested on
PX4 holybro-can-gps-v1

glitch free

F4, F7, H7 HW

image

   This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source. This
   produced a 430 nS glich on a F4 @168 Mhz. It was a enough
   to corrupt an I2C device with a bus monitor.
   This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
   This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
   The stm32_gpiosetevent calls stm32_configgpio. So
   the pin is infact restored to the SDMMC/SDIO D0.

   The seconday init, dropped interrupts in a debug
   build with HW stack checking on after the GPIO glich
   fixes and that was how it was detected.
@davids5
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davids5 commented Sep 21, 2021

All: You may want to review the order of operations on the GPIO code for the SoC you work on, I think this may systemic.

@xiaoxiang781216 xiaoxiang781216 merged commit a9ff808 into apache:master Sep 22, 2021
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3 participants