xtensa: use swint to swith context #5336

zhuyanlinzyl · 2022-01-25T09:12:05Z

Summary

Reason for use sw-interrupt as syscall interrupt:
The xtensa syscall instruction can cause SYSCALL interrupt.
But SYSCALL interrupt is same interrupt level with level-one
interrupt.
Nuttx swint can enter enter_critical_section and generate interrupt.

Impact

No

Testing

Testing ostest pass on Xtensa core.

masayuki2009 · 2022-01-26T01:35:26Z

xtensa_reprioritizertr.c:(.text.up_reprioritize_rtr+0x72): undefined reference to `xtensa_switchcontext'

masayuki2009 · 2022-02-09T00:22:17Z

@zhuyanlinzyl
Please rebase the branch to the latest master?

masayuki2009 · 2022-02-09T05:45:55Z

====================================================================================
Configuration/Tool: esp32s3-devkit/nsh
------------------------------------------------------------------------------------
  Cleaning...
  Configuring...
  Building NuttX...
xtensa-esp32s3-elf-ld: /github/workspace/sources/nuttx/staging/libarch.a(xtensa_blocktask.o):(.literal.up_block_task+0x0): undefined reference to `xtensa_switchcontext'
xtensa-esp32s3-elf-ld: /github/workspace/sources/nuttx/staging/libarch.a(xtensa_blocktask.o): in function `up_block_task':
/github/workspace/sources/nuttx/arch/xtensa/src/common/xtensa_blocktask.c:133: undefined reference to `xtensa_switchcontext'
xtensa-esp32s3-elf-ld: /github/workspace/sources/nuttx/staging/libarch.a(xtensa_releasepending.o): in function `up_release_pending':
/github/workspace/sources/nuttx/arch/xtensa/src/common/xtensa_releasepending.c:108: undefined reference to `xtensa_switchcontext'
xtensa-esp32s3-elf-ld: /github/workspace/sources/nuttx/staging/libarch.a(xtensa_unblocktask.o): in function `up_unblock_task':
/github/workspace/sources/nuttx/arch/xtensa/src/common/xtensa_unblocktask.c:122: undefined reference to `xtensa_switchcontext'
xtensa-esp32s3-elf-ld: /github/workspace/sources/nuttx/staging/libarch.a(xtensa_reprioritizertr.o): in function `up_reprioritize_rtr':
/github/workspace/sources/nuttx/arch/xtensa/src/common/xtensa_reprioritizertr.c:156: undefined reference to `xtensa_switchcontext'
make[1]: *** [Makefile:119: nuttx] Error 1
make: *** [tools/Unix.mk:510: nuttx] Error 2
make: Target 'all' not remade because of errors.

masayuki2009 · 2022-02-09T05:47:25Z

esp32-devkitc:nsh and esp32-devkitc:smp do not work with QEMU.

zhuyanlinzyl · 2022-02-10T02:34:54Z

esp32s3 is a newly added Xtensa chip.

I added the esp32s3 Make.defs agiain.

Please review again @masayuki2009

masayuki2009 · 2022-02-10T03:29:44Z

@zhuyanlinzyl
Did you test this PR with QEMU?
You need to use the latest espressif/qemu which @Ouss4 commented in #5407

zhuyanlinzyl · 2022-02-10T03:51:54Z

@masayuki2009 No, I only tested in our board with xtensa chip.

As QEMU do not work with esp32,

This patch need @Ouss4 review and tested in there board.

masayuki2009 · 2022-02-10T03:54:44Z

As QEMU do not work with esp32,

@zhuyanlinzyl
Actually, espressif/qemu works for esp32-devkitc:nsh and esp32-devkitc:smp
Please read #5407 as well.

zhuyanlinzyl · 2022-02-10T04:34:31Z

Thanks，I setup the esp32 QEMU environment ant test patch on it @masayuki2009

zhuyanlinzyl · 2022-02-10T06:25:20Z

hi @Ouss4 , I'd like to known how to get the esp toolchain xtensa-esp32-elf-gcc ?

Ouss4 · 2022-02-10T07:54:13Z

@zhuyanlinzyl all the toolchains from Espressif can be downloaded from https://github.com/espressif/crosstool-NG/releases

zhuyanlinzyl · 2022-02-15T08:30:49Z

hi @Ouss4 :

I just test this patch in Qemu, And add software interrupt (bit 29, software interrupt 1) for esp32.
Now esp32-devkitc:nsh work fine.

zyl@zyl:~/nuttx$ qemu-system-xtensa -nographic -machine esp32 -smp 2 -drive file=./nuttx.merged.bin,if=mtd,format=raw
==1256274==WARNING: ASan doesn't fully support makecontext/swapcontext functions and may produce false positives in some cases!
Adding SPI flash device
ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:6604
ho 0 tail 12 room 4
load:0x40078000,len:14780
load:0x40080400,len:3792
entry 0x40080694
I (1015) boot: ESP-IDF v4.4 2nd stage bootloader
I (1030) boot: compile time 19:32:08
I (1050) boot: chip revision: 0
I (1065) boot.esp32: SPI Speed      : 40MHz
I (1068) boot.esp32: SPI Mode       : DIO
I (1070) boot.esp32: SPI Flash Size : 4MB
I (1092) boot: Enabling RNG early entropy source...
I (1124) boot: Partition Table:
I (1125) boot: ## Label            Usage          Type ST Offset   Length
I (1128) boot:  0 factory          factory app      00 00 00010000 00100000
I (1145) boot: End of partition table
I (1164) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=01aech (  6892) map
I (1208) esp_image: segment 1: paddr=00011b14 vaddr=3ffb1320 size=000dch (   220) load
I (1238) esp_image: segment 2: paddr=00011bf8 vaddr=40080000 size=0174ch (  5964) load
I (1282) esp_image: segment 3: paddr=0001334c vaddr=00000000 size=0cccch ( 52428) 
I (1393) esp_image: segment 4: paddr=00020020 vaddr=400d0020 size=0f2dch ( 62172) map
I (1525) boot: Loaded app from partition at offset 0x10000
I (1529) boot: Disabling RNG early entropy source...

NuttShell (NSH) NuttX-10.2.0
nsh> ps
  PID GROUP PRI POLICY   TYPE    NPX STATE    EVENT     SIGMASK   STACK COMMAND
    0     0   0 FIFO     Kthread N-- Ready              00000000 003040 Idle Task
    1     1 100 RR       Task    --- Running            00000000 002000 nsh_main

But in esp32-devkitc:smp crash in the CPU1 initialize

zyl@zyl:~/nuttx$ qemu-system-xtensa -nographic -machine esp32 -smp 2 -drive file=./nuttx.merged.bin,if=mtd,format=raw
==1343754==WARNING: ASan doesn't fully support makecontext/swapcontext functions and may produce false positives in some cases!
Adding SPI flash device
ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:6604
ho 0 tail 12 room 4
load:0x40078000,len:14780
load:0x40080400,len:3792
entry 0x40080694
I (1004) boot: ESP-IDF v4.4 2nd stage bootloader
I (1019) boot: compile time 19:32:08
I (1038) boot: chip revision: 0
I (1054) boot.esp32: SPI Speed      : 40MHz
I (1056) boot.esp32: SPI Mode       : DIO
I (1058) boot.esp32: SPI Flash Size : 4MB
I (1082) boot: Enabling RNG early entropy source...
I (1112) boot: Partition Table:
I (1114) boot: ## Label            Usage          Type ST Offset   Length
I (1118) boot:  0 factory          factory app      00 00 00010000 00100000
I (1134) boot: End of partition table
I (1152) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=08700h ( 34560) map
I (1242) esp_image: segment 1: paddr=00018728 vaddr=3ffb3ce0 size=00100h (   256) load
I (1271) esp_image: segment 2: paddr=00018830 vaddr=40080000 size=01c58h (  7256) load
I (1319) esp_image: segment 3: paddr=0001a490 vaddr=00000000 size=05b88h ( 23432) 
I (1385) esp_image: segment 4: paddr=00020020 vaddr=400d0020 size=170d0h ( 94416) map
I (1585) boot: Loaded app from partition at offset 0x10000
I (1587) boot: Disabling RNG early entropy source...
[CPU1] xtensa_appcpu_start 184
[CPU1] esp32_cpuint_initialize 719
[CPU1] xtensa_appcpu_start 207
[CPU1] xtensa_appcpu_start 227
[CPU1] xtensa_user_panic: User Exception: EXCCAUSE=0000 task: CPU1 IDLE
[CPU1] xtensa_dumpstate: CPU1:
[CPU1] xtensa_registerdump:    PC: 400d5d71    PS: 00060530
[CPU1] xtensa_registerdump:    A0: 80007c18    A1: 3ffb3ce0    A2: 00000000    A3: 3ffb0170
[CPU1] xtensa_registerdump:    A4: 00400115    A5: 00000000    A6: 00000000    A7: 00000000
[CPU1] xtensa_registerdump:    A8: 00000000    A9: 00000000   A10: 00000000   A11: 00000000
[CPU1] xtensa_registerdump:   A12: 00000000   A13: 00000000   A14: 00000000   A15: 00000000
[CPU1] xtensa_registerdump:   SAR: 00000000 CAUSE: 00000000 VADDR: 00000000
[CPU1] xtensa_registerdump:  LBEG: 00000000  LEND: 00000000  LCNT: 00000000
[CPU1] xtensa_registerdump:  TMP0: 00000000  TMP1: 00000000
[CPU1] xtensa_dumpstate: sp:     3ffb12e4
[CPU1] xtensa_dumpstate: IRQ stack:
[CPU1] xtensa_dumpstate:   base: 3ffb0b84
[CPU1] xtensa_dumpstate:   size: 00000800

[CPU1] xtensa_dumpstate:   used: 000002ec
[CPU1] xtensa_stackdump: 3ffb12e0: 3f4001bc 00000000 3ffb1344 00000000 3ffNutbtShell3 (NSH)a NuttX-1b0.2.0
0 3ffb3100 3ffb1304 00000008
[CPU1] xtensa_stackdump: 3ffb1300: deadbeef 3ffb2498 0000ns0h>  Ke0 3ffb0b84 3ffb0170 800d5116 3ffb1344 00000000
[CPU1] xtensa_stackdump: 3ffb1320: 3ffb3ab0 3f4001e8 00000000 3ffb02b0 3f400115 40080871 3ffb1364 00000000
[CPU1] xtensa_stackdump: 3ffb1340: 3ffb3ab0 800df504 3ffb3c50 00000000 3f400115 00040023 3ffb1384 3ffb3ab0
[CPU1] xtensa_stackdump: 3ffb1360: 00000012 800d5d71 3ffb3cd0 00000001 3ffb01ec deadbeef deadbeef deadbeef
[CPU1] xtensa_dumpstate: sp:     3ffb3ce0
[CPU1] xtensa_dumpstate: User stack:
[CPU1] xtensa_dumpstate:   base: 3ffb3100
[CPU1] xtensa_dumpstate:   size: 00000be0
[CPU1] xtensa_dumpstate:   used: 00000270
[CPU1] xtensa_dumpstate: ERROR: Stack pointer is not within allocated stack
[CPU1] xtensa_stackdump: 3ffb3a80: deadbeef deadbeef deadbeef deadbeef 00000109 deadbeef deadbeef deadbeef
[CPU1] xtensa_stackdump: 3ffb3aa0: deadbeef deadbeef deadbeef deadbeef 400d5d71 00060530 80007c18 3ffb3ce0
[CPU1] xtensa_stackdump: 3ffb3ac0: 00000000 3ffb0170 3f400115 3f4005a1 3ff9eae0 3ff9eac9 800d5d71 3ffb3cd0
[CPU1] xtensa_stackdump: 3ffb3ae0: 00000001 3ffb01ec 20000000 000000e3 00060520 00000000 00000004 400e5b40
[CPU1] xtensa_stackdump: 3ffb3b00: fffffffc 00000000 400d4f28 400d4f57 0000001f 40080844 3ffb3ab0 3f4086f0
[CPU1] xtensa_stackdump: 3ffb3b20: 800d3b92 3ffb3b50 3ffb3c20 0000000a fffffffc 00000000 00000000 00000003
[CPU1] xtensa_stackdump: 3ffb3b40: 800d422c 3ffb3b70 00000018 400e5b40 fffffffc 00000000 00000000 00000003
[CPU1] xtensa_stackdump: 3ffb3b60: 800e5b3a 3ffb3bf0 3ffb3c20 3f400115 3f323237 3ffb3bb0 3ffb3c00 3f4086f0
[CPU1] xtensa_stackdump: 3ffb3b80: 3f4086f8 3ffb3be0 0000000c 00000000 800e5b2b 3ffb3bd0 3ffb3c20 3f4086f0
[CPU1] xtensa_stackdump: 3ffb3ba0: 3ffb3cc0 3ffb3ca0 00000008 3ffb3cc0 00000003 00000000 00000000 00000000
[CPU1] xtensa_stackdump: 3ffb3bc0: 3ffb3c20 3ffb3c20 00000000 3f400115 3f40011c 3ffb3ca0 00000010 00000000
[CPU1] xtensa_stackdump: 3ffb3be0: 800df4e0 3ffb3c20 00000007 3f400115 00000008 00000000 00000000 3f400115
[CPU1] xtensa_stackdump: 3ffb3c00: 3ffb3cc0 3ffb3ca0 00000008 00000000 800df504 3ffb3c50 00000000 3f400115
[CPU1] xtensa_stackdump: 3ffb3c20: 400e5b40 3ffb3c70 400e6814 0000001f 3ffb3c50 3ffb02d0 00060522 00000000
[CPU1] xtensa_stackdump: 3ffb3c40: 800d5d6b 3ffb3c90 00000000 3f400115 3ffb3cc0 3ffb3ca0 00000008 00000000
[CPU1] xtensa_stackdump: 3ffb3c60: 3ffb3cc0 3ffb3ca0 00000008 3f400115 3ffb3cc0 3ffb3ca0 00000008 00000001
[CPU1] xtensa_stackdump: 3ffb3c80: 80007c18 3ffb3ce0 00000000 3ffb0170 3ffb3cc0 3ffb3ca0 00000008 deadbeef
[CPU1] xtensa_stackdump: 3ffb3ca0: 3f40011d 000002cf 3f4005a1 000000e3 00060520 00000000 00000000 3ffb0170
[CPU1] xtensa_stackdump: 3ffb3cc0: 3f4005a1 000000e3 00060520 00000000 40000740 3ffe7dc0 400d5cd0 3ffe4310
[CPU1] xtensa_showtasks:    PID    PRI      USED     STACK   FILLED    COMMAND
[CPU1] xtensa_showtasks:   ----   ----       812      2048    39.6%    irq
[CPU1] xtensa_dump_task:      0      0      1072      3040    35.2%    CPU0 IDLE
[CPU1] xtensa_dump_task:      1      0       624      3040    20.5%    CPU1 IDLE
[CPU1] xtensa_dump_task:      2    100      1216      2000    60.8%    nsh_main

nsh> ps
  PID GROUP CPU PRI POLICY   TYPE    NPX STATE    EVENT     SIGMASK   STACK   USED  FILLED COMMAND
    0     0   0   0 FIFO     Kthread N-- Assigned           00000000 003040 001072  35.2%  CPU0 IDLE
    1     1   1   0 FIFO     Kthread N-- Running            00000000 003040 000624  20.5%  CPU1 IDLE
    2     2   0 100 RR       Task    --- Running            00000000 002000 001856  92.8%! nsh_main

Could you give me some advice?

arch/xtensa/include/syscall.h

zhuyanlinzyl · 2022-02-15T11:44:13Z

@Ouss4 I think I have find the reason:

CPU1 have not generate swi interrupt at all.

As esp32 only have two software interrupt bit:

#define ESP32_CPUINT_SOFTWARE0 7
#define ESP32_CPUINT_SOFTWARE1 29

I select ESP32_CPUINT_SOFTWARE1 for CPU0 swi interrupt .

As the ESP32_CPUINT_SOFTWARE1 have interrupt level-3.
But ESP32_CPUINT_SOFTWARE0 is interrupt level-1.

I'd like to know, CPU1 must use another sw interrupt pin to generate interrupt in ESP32?

Ouss4 · 2022-02-15T12:31:52Z

@zhuyanlinzyl ESP32 should have a software interrupt per CPU. I think the issue here is that the software interrupt was enabled only for CPU0.
In this case we need to map the software interrupt twice (one for each CPU) and enable it twice (one for each CPU).

Ouss4 · 2022-02-15T12:36:33Z

Note that enabling a CPU interrupt must be done from the specific CPU. We cannot enable CPU1's interrupts from CPU0.
In this case then, I believe we need:

A call to g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1); This maps CPU1 interrupt. This can be done from any CPU.
During CPU1 startup we call up_enable_irq(XTENSA_IRQ_SWINT);.

zhuyanlinzyl · 2022-02-15T13:16:51Z

@Ouss4
I have try in this patch.

--- a/arch/xtensa/src/esp32/esp32_irq.c
+++ b/arch/xtensa/src/esp32/esp32_irq.c
@@ -472,6 +472,7 @@ void up_irqinitialize(void)
 #endif
 
   g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32_CPUINT_SOFTWARE1);
+  g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1);
 
   /* Initialize CPU interrupts */

 --- a/arch/xtensa/src/esp32/esp32_cpustart.c
 +++ b/arch/xtensa/src/esp32/esp32_cpustart.c
@@ -193,6 +193,14 @@ void xtensa_appcpu_start(void)
 
   xtensa_attach_fromcpu0_interrupt();
 
+  /* Attach the timer interrupt */
+
+  irq_attach(XTENSA_IRQ_SWINT, (xcpt_t)xtensa_swint, NULL);
+
+  /* Enable the timer 0 CPU interrupt. */
+
+  up_enable_irq(XTENSA_IRQ_SWINT);
+

but ESP32_CPUINT_SOFTWARE1 only map to CPU1 finally.

As g_irqmap is not g_irqmap[CONFIG_SMP_NCPUS]

So I think must use separate SWI interrupt pin for each CPU?

Ouss4 · 2022-02-15T13:54:51Z

but ESP32_CPUINT_SOFTWARE1 only map to CPU1 finally.

I think your right, the second one (which ever CPU is) overwrites the first one, this is the same case as the GPIO interrupt where the IRQ is the same... We gonna have to treat these separately.

zhuyanlinzyl · 2022-02-16T02:49:47Z

@Ouss4 :

but ESP32 chip only have two swi interrupt:

#define ESP32_CPUINT_SOFTWARE0 7
#define ESP32_CPUINT_SOFTWARE1 29

only ESP32_CPUINT_SOFTWARE1 can use for nuttx swi, what else interrupt pin can I use?

Ouss4 · 2022-02-16T09:09:04Z

but ESP32 chip only have two swi interrupt:

These are internal CPU interrupts, which means each CPU has both ESP32_CPUINT_SOFTWARE0 and ESP32_CPUINT_SOFTWARE1. They have the same interrupt number but controlled from each CPU's registers. For instance INTENABLE of CPU0 enables/disables ESP32_CPUINT_SOFTWARE0/ESP32_CPUINT_SOFTWARE1 of CPU0.
The thing that I see is going to be a bit messy is how we dispatch the interrupts. Since they have the same numbers so in NuttX they will have the same irq number.

EDIT: On a second thought, I don't think this will get that messy. I had the GPIO example in my mind, but this is a bit different. The only issue is enabling the interrupt using up_enable_irq, because this function tries to get the CPU from the map. If we only need to enable the software interrupt once and never disable it again, I think we can bypass this.

zhuyanlinzyl · 2022-02-17T03:47:06Z

@Ouss4 :

These are internal CPU interrupts, which means each CPU has both ESP32_CPUINT_SOFTWARE0 and ESP32_CPUINT_SOFTWARE1. They have the same interrupt number but controlled from each CPU's registers.

So each CPU have separate internal interrupts，Such as ESP32_CPUINT_SOFTWARE1 and
ESP32_CPUINT_TIMER0

Then I think the g_irqmap must be g_irqmap[CONFIG_SMP_NCPUS] for internal interrupts.
Is my understanding correct?

The thing that I see is going to be a bit messy is how we dispatch the interrupts. Since they have the same numbers so in NuttX they will have the same irq number.

I don't think dispatch interrupts is a problem. As every CPU only have one interrupt per number , They handle their own interrupts independently.

I have modify up_enable_irq with this patch

   if (irq < XTENSA_NIRQ_INTERNAL)
     {
-      /* Enable the CPU interrupt now for internal CPU. */
 
+      /* Enable the CPU interrupt now for internal CPU. */
+      if ((irq == 4) && (up_cpu_index() == 0))
+        {
+          cpu = 0;
+        }
       xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
     }

Then the smp config work well.

zyl@zyl:~/nuttx$ qemu-system-xtensa -nographic -machine esp32 -smp 2 -drive file=./nuttx.merged.bin,if=mtd,format=raw
==3509606==WARNING: ASan doesn't fully support makecontext/swapcontext functions and may produce false positives in some cases!
Adding SPI flash device
ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:6604
ho 0 tail 12 room 4
load:0x40078000,len:14780
load:0x40080400,len:3792
entry 0x40080694
I (1017) boot: ESP-IDF v4.4 2nd stage bootloader
I (1031) boot: compile time 19:32:08
I (1053) boot: chip revision: 0
I (1069) boot.esp32: SPI Speed      : 40MHz
I (1072) boot.esp32: SPI Mode       : DIO
I (1074) boot.esp32: SPI Flash Size : 4MB
I (1097) boot: Enabling RNG early entropy source...
I (1129) boot: Partition Table:
I (1130) boot: ## Label            Usage          Type ST Offset   Length
I (1132) boot:  0 factory          factory app      00 00 00010000 00100000
I (1150) boot: End of partition table
I (1169) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=08708h ( 34568) map
I (1270) esp_image: segment 1: paddr=00018730 vaddr=3ffb3ce0 size=00100h (   256) load
I (1305) esp_image: segment 2: paddr=00018838 vaddr=40080000 size=01c58h (  7256) load
I (1357) esp_image: segment 3: paddr=0001a498 vaddr=00000000 size=05b80h ( 23424) 
I (1428) esp_image: segment 4: paddr=00020020 vaddr=400d0020 size=170e0h ( 94432) map
I (1632) boot: Loaded app from partition at offset 0x10000
I (1636) boot: Disabling RNG early entropy source...
NuttShell (NSH) NuttX-10.2.0
nsh> ps
  PID GROUP CPU PRI POLICY   TYPE    NPX STATE    EVENT     SIGMASK   STACK   USED  FILLED COMMAND
    0     0   0   0 FIFO     Kthread N-- Assigned           00000000 003040 000976  32.1%  CPU0 IDLE
    1     1   1   0 FIFO     Kthread N-- Running            00000000 003040 000640  21.0%  CPU1 IDLE
    2     2   0 100 RR       Task    --- Running            00000000 002000 001840  92.0%! nsh_main

arch/xtensa/src/esp32/esp32_irq.c

arch/xtensa/include/esp32/irq.h

Ouss4 · 2022-02-18T00:07:17Z

@zhuyanlinzyl can you please try #5536
The second commit bypasses the map when it comes to internal interrupts and just uses the current CPU.

zhuyanlinzyl · 2022-02-18T03:40:41Z

@Ouss4 ,

I try #5536 it work well on my QEMU esp32-smp.
You can have a test and merge that PR

zhuyanlinzyl · 2022-02-18T06:42:29Z

hi, @Ouss4 @masayuki2009 @gustavonihei

I think this PR contain two many different changes.

I have spit into three:

#5541: modify xtensa svc to swi. This is first and not depend on each other.
#5542: add esp32 software interrupt.

Please review These PR before this.

arch/xtensa/include/syscall.h

xiaoxiang781216 · 2022-02-23T14:06:21Z

@zhuyanlinzyl do we still need this patch?

Ouss4 · 2022-02-23T22:43:54Z

@zhuyanlinzyl do we still need this patch?

We do, this is the context switching part. The two other PRs have part of this PR, when both are merged this need to be rebased.

Ouss4 · 2022-02-23T23:07:32Z

Both PRs are merged now. @zhuyanlinzyl can you please rebase and fix the conflicts.

For up_irq_disable, use XCHAL_EXCM_LEVEL For up_irq_save, use XCHAL_IRQ_LEVEL. Then we can use svcall in enter_crritical_section. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

zhuyanlinzyl · 2022-02-24T03:23:58Z

hi, @masayuki2009 @Ouss4 :
I have rebase this patch, and test on qemu esp32 and qemu esp32:smp with ostest.

Please review and test again.

zhuyanlinzyl · 2022-02-24T13:36:06Z

@Ouss4 : Could you please review again?

arch/xtensa/src/common/xtensa_context.S

Reason for use sw-interrupt as syscall interrupt: The xtensa `syscall` instruction can cause SYSCALL interrupt. But SYSCALL interrupt is same interrupt level with level-one interrupt. Nuttx swint can enter `enter_critical_section` and gerenate interrupt. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

zhuyanlinzyl · 2022-02-25T03:07:30Z

@Ouss4 Yes, isync is enough. I have test on qemu esp32 and our board.

Ouss4 · 2022-02-25T08:24:43Z

I pushed a branch internally with this PR. All tests passed except S2 where #5609 is needed.

zhuyanlinzyl · 2022-02-25T09:01:44Z

Okay, could we can review and merge this PR? @Ouss4 @gustavonihei

Ouss4

LGTM!

zhuyanlinzyl mentioned this pull request Jan 25, 2022

xtensa: add svccall handler and use svc call in context switch #5261

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zhuyanlinzyl force-pushed the svc branch from ada58e9 to 000bb86 Compare January 25, 2022 13:10

zhuyanlinzyl force-pushed the svc branch from 000bb86 to c102a98 Compare January 27, 2022 03:22

acassis requested review from masayuki2009 and Ouss4 February 8, 2022 12:43

zhuyanlinzyl force-pushed the svc branch from c102a98 to b5dcdde Compare February 9, 2022 03:12

zhuyanlinzyl force-pushed the svc branch from b5dcdde to 129b0f6 Compare February 10, 2022 02:33

zhuyanlinzyl force-pushed the svc branch from 129b0f6 to e3aee9e Compare February 15, 2022 08:25

Ouss4 reviewed Feb 15, 2022

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zhuyanlinzyl force-pushed the svc branch from e3aee9e to 968851e Compare February 15, 2022 11:25

gustavonihei reviewed Feb 17, 2022

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arch/xtensa/src/esp32/esp32_irq.c Outdated Show resolved Hide resolved

Ouss4 reviewed Feb 17, 2022

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zhuyanlinzyl force-pushed the svc branch from 968851e to e2089da Compare February 18, 2022 03:41

zhuyanlinzyl force-pushed the svc branch from e2089da to 601ce26 Compare February 18, 2022 11:17

Ouss4 reviewed Feb 18, 2022

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arch/xtensa/include/syscall.h Outdated Show resolved Hide resolved

xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO

41b0a6e

For up_irq_disable, use XCHAL_EXCM_LEVEL For up_irq_save, use XCHAL_IRQ_LEVEL. Then we can use svcall in enter_crritical_section. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

zhuyanlinzyl force-pushed the svc branch 2 times, most recently from 854bc0f to e052fcf Compare February 24, 2022 03:21

zhuyanlinzyl force-pushed the svc branch from e052fcf to b0c3259 Compare February 24, 2022 08:05

Ouss4 reviewed Feb 24, 2022

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arch/xtensa/src/common/xtensa_context.S Outdated Show resolved Hide resolved

Ouss4 mentioned this pull request Feb 24, 2022

arch/xtensa/esp32s2_irq.c: Correctly enable the software interrupt. #5609

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zhuyanlinzyl force-pushed the svc branch from b0c3259 to 7398e59 Compare February 25, 2022 03:06

Ouss4 approved these changes Feb 25, 2022

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xiaoxiang781216 approved these changes Feb 25, 2022

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xiaoxiang781216 merged commit fbc1da9 into apache:master Feb 25, 2022

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xtensa: use swint to swith context #5336

xtensa: use swint to swith context #5336

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xtensa: use swint to swith context #5336

xtensa: use swint to swith context #5336

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