arch/pic32mz: Serial TIOCxBRK BSD-compatible BREAK support #8550
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In the lower half UART driver for PIC32MZ architecture, adding the TIOCxBRK ioctl calls, which allow an application to transmit a UART line BREAK signal. This architecture does not support BSD-style BREAK in hardware so our implementation follows the precedent set in STM32, GD32, and Kinetis architectures: By default, if only PIC32MZ_UART_BREAKS is configured, we produce the hardware-native BREAK, which lasts for 12 bit lengths; if, in addition, PIC32MZ_SERIALBRK_BSDCOMPAT is configured, we generate a BSD-style BREAK by putting the TX pin in GPIO mode and driving it low "manually" until told to stop. * arch/mips/src/pic32mz/Kconfig (config PIC32MZ_UART_BREAKS): New. Appears as CONFIG_PIC32MZ_UART_BREAKS in code. (config PIC32MZ_SERIALBRK_BSDCOMPAT): New. Appears as CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT in code. * arch/mips/src/pic32mz/hardware/pic32mz_pps.h (__PPS_OUTPUT_REGADDR_TO_GPIO, PPS_OUTPUT_REGADDR_TO_GPIO): New macros to automatically determine the GPIO port and pin from the corresponding PPS (Peripheral Pin Select) define. Since there is a one-to-one correspondence between PPS output mappings and a single port and pin, these macros avoid writing redundant pin mappings. We use this when switching the TX pin from UART to GPIO to generate the BREAK and we could use it in other peripheral drivers in the future to override hardware behavior. * arch/mips/src/pic32mz/pic32mz_serial.c (struct up_dev_s): Add new field 'brk' to indicate line break in progress when built with PIC32MZ_UART_BREAKS. If generating BSD- compatible BREAKs, also add tx_gpio, tx_pps_reg, and tx_pps_val, to let us toggle the pin between UART and GPIO modes. (up_ioctl): Add cases for TIOCSBRK and TIOCCBRK to turn BREAK on and off, with both hardware-native and BSD-compatible implementations. This is similar to the STM32F7 implementation. (up_txint): Block enabling TX interrupt if line break in progress. This is similar to the STM32F7 implementation.
xiaoxiang781216
approved these changes
Feb 17, 2023
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Summary
In the lower half UART driver for PIC32MZ architecture, adding the
TIOCxBRKioctl calls (TIOCSBRKandTIOCCBRK). These allow an application to transmit a BREAK (either hardware-native or BSD compatible).This architecture does not support BSD-style BREAK in hardware so our implementation follows the precedent set in STM32, GD32, and Kinetis architectures: By default, if only
PIC32MZ_UART_BREAKSis configured, we produce the hardware-native BREAK, which lasts for 12 bit lengths on this architecture; if, in addition,PIC32MZ_SERIALBRK_BSDCOMPATis also configured, we generate a BSD-style BREAK by putting the TX pin in GPIO mode and driving it "manually" until told to stop.Impact
When
PIC32MZ_UART_BREAKSis activated,TIOCSBRKandTIOCCBRKioctl calls are supported on PIC32MZ architectures. WhenPIC32MZ_SERIALBRK_BSDCOMPATis also activated, the ioctl calls are BSD-compatible. When not activated, no effect.Testing
Works on custom board.
nxstyle.