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bin
blink
clk_div8
compare8
counter8
fibonacci
fibonacci_mem_uart
fifo
fm_out
ice
ip
lib/python
mem_uart
multiply_mem_uart
oc8051
oc8051_ice
parity_bit
phase_out
picorv32
pid
pll_blink
prime
prng
prng_parallel
pwm_in
pwm_out
ram
ram_uart
spi
spi_slave
spi_slave_regs
switch_test
timer
uart2gpio
uart2pwm
uart_ice
uart_loopback
uart_rx
uart_tx
up
up2
up2_alu
up2_code
up2_fetch
up2_mem
up2_pc_stack
up2_reg_stack
vga_out
watchdog
.gitignore
README.md
list.txt
make_list.py

README.md

Verilog

  • Icarus
  • YOSYS 0.6

Simulation

  • To run a simulation $./bin/runsim -m <path/to/module/folder> -s

  • To view the waves $./bin/runsim -m <path/to/module/folder> -w