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Implement a MIPS 5-stage pipelined CPU using Vivado

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计算机体系结构实验

在vivado上实现了MIPS流水线CPU, 内容包括:

  • lab01: LED Flow Water Light
  • lab02: 4-bit Adder
  • lab03: MIPS ALU
  • lab04: Register and memory
  • lab05: a single cycle CPU with 16 instructions(add, sub, and, or, addi, andi, ori, slt, lw, sw, beq, j, jal, jr, sll, srl)
  • lab06: pipelining with stall, forwarding, predict-not-taken and 31 instructions

仅供参考,请勿抄袭

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