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Add external cellular RAM
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@atgreen
atgreen committed Mar 17, 2013
1 parent 0190d61 commit 209827b
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Showing 6 changed files with 322 additions and 248 deletions.
85 changes: 45 additions & 40 deletions cores/MoxieLite/moxielite.vhd
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Expand Up @@ -32,7 +32,9 @@ END moxielite;
ARCHITECTURE behavior OF moxielite IS

signal reset : std_logic;


signal Adebug_o : std_logic_vector(7 downto 0);

-- Program counter
signal PC : std_logic_vector(31 downto 0) := BOOT_ADDRESS;
signal PC_plus_2 : std_logic_vector(31 downto 0);
Expand Down Expand Up @@ -620,12 +622,14 @@ BEGIN

elsif rising_edge(clock) then

debug_o <= PC(15 downto 8);

-- Handle state
case state_resolved is

when state_reset =>
state <= state_fetch_pre;
debug_o <= "00000000";
Adebug_o <= "00000000";

when state_fetch_pre =>

Expand All @@ -635,7 +639,7 @@ BEGIN
reg_dump_index <= "00000";
state <= state_debug;
end if;
debug_o <= "00000001";
Adebug_o <= "00000001";

when state_debug =>

Expand Down Expand Up @@ -674,7 +678,7 @@ BEGIN
state <= state_fetch_wait;
have_imm <= '0';
have_deref <= '0';
debug_o <= "00000010";
Adebug_o <= "00000010";

when state_fetch_wait =>

Expand All @@ -692,11 +696,11 @@ BEGIN
state <= state_decode;

end if;
debug_o <= "00000011";
Adebug_o <= "00000011";

when state_decode =>
-- Pseudo state to resolve loading immediate operand + deref source pointer
debug_o <= "00000100";
Adebug_o <= "00000100";
null;

when state_read_imm_setup =>
Expand All @@ -707,7 +711,7 @@ BEGIN
data_byte_count <= "100";
state_next <= state_latch_imm;
state <= state_load_memcycle;
debug_o <= "00000101";
Adebug_o <= "00000101";

when state_latch_imm =>

Expand All @@ -717,7 +721,7 @@ BEGIN
have_imm <= '1';
imm_reg <= data_bswap;
state <= state_decode;
debug_o <= "00000110";
Adebug_o <= "00000110";

when state_deref_ptr_setup =>

Expand All @@ -729,25 +733,25 @@ BEGIN
data_byte_count <= ptr_size;
state_next <= state_latch_deref;
state <= state_load_memcycle;
debug_o <= "00000111";
Adebug_o <= "00000111";

when state_latch_deref =>

-- Finished reading dereffed value
-- Store it and continue
have_deref <= '1';
state <= state_decode;
debug_o <= "00001000";
Adebug_o <= "00001000";

when state_load_pre =>

state <= state_load_memcycle;
debug_o <= "00001001";
Adebug_o <= "00001001";

when state_load_memcycle =>

state <= state_load_wait;
debug_o <= "00001010";
Adebug_o <= "00001010";

when state_load_wait =>

Expand Down Expand Up @@ -817,17 +821,17 @@ BEGIN
end if;

end if;
debug_o <= "00001011";
Adebug_o <= "00001011";

when state_store_pre =>

state <= state_store_memcycle;
debug_o <= "00001100";
Adebug_o <= "00001100";

when state_store_memcycle =>

state <= state_store_wait;
debug_o <= "00001101";
Adebug_o <= "00001101";

when state_store_wait =>

Expand All @@ -843,12 +847,12 @@ BEGIN
end if;

end if;
debug_o <= "00001110";
Adebug_o <= "00001110";

when state_execute =>

-- pseudo state, never reached, resolves to one of the states below
debug_o <= "00001111";
Adebug_o <= "00001111";
Null;

when state_execute_cmp =>
Expand All @@ -859,7 +863,7 @@ BEGIN
SFlag <= alu_SFlag;
CFlag <= alu_CFlag;
state <= state_fetch_pre;
debug_o <= "00010000";
Adebug_o <= "00010000";

when state_execute_alu =>

Expand All @@ -868,7 +872,7 @@ BEGIN

-- Continue with next instruction
state <= state_fetch_pre;
debug_o <= "00010001";
Adebug_o <= "00010001";

when state_execute_store =>

Expand All @@ -879,7 +883,7 @@ BEGIN
data_byte_count <= ptr_size;
state_next <= state_fetch_pre;
state <= state_store_memcycle;
debug_o <= "00010010";
Adebug_o <= "00010010";

when state_execute_push =>

Expand All @@ -891,7 +895,7 @@ BEGIN
state <= state_store_memcycle;

regfile(to_integer(unsigned(reg_A))) <= alu_result;
debug_o <= "00010011";
Adebug_o <= "00010011";

when state_execute_pop =>

Expand All @@ -903,19 +907,19 @@ BEGIN
state <= state_load_memcycle;

regfile(to_integer(unsigned(reg_A))) <= alu_result;
debug_o <= "00010100";
Adebug_o <= "00010100";

when state_execute_pop_2 =>

regfile(to_integer(unsigned(reg_B))) <= data_bswap;
state <= state_fetch_pre;
debug_o <= "00010101";
Adebug_o <= "00010101";

when state_execute_nop =>

-- Do nothing, this should be easy...
state <= state_fetch_pre;
debug_o <= "00010110";
Adebug_o <= "00010110";

when state_execute_bcc =>

Expand All @@ -925,14 +929,14 @@ BEGIN
end if;

state <= state_fetch_pre;
debug_o <= "00010111";
Adebug_o <= "00010111";

when state_execute_jmp =>

-- Branch unconditionally
PC <= operand_A(31 downto 1) & '0';
state <= state_fetch_pre;
debug_o <= "00011000";
Adebug_o <= "00011000";

when state_execute_jsr =>

Expand All @@ -946,7 +950,7 @@ BEGIN
data_byte_count <= "100";
state_next <= state_execute_jsr_2;
state <= state_store_memcycle;
debug_o <= "00011001";
Adebug_o <= "00011001";

when state_execute_jsr_2 =>

Expand All @@ -964,7 +968,7 @@ BEGIN

-- Jump!
PC <= operand_A(31 downto 1) & '0';
debug_o <= "00011010";
Adebug_o <= "00011010";

when state_execute_ret =>

Expand All @@ -977,7 +981,7 @@ BEGIN
state <= state_load_memcycle;

regfile(1) <= regfile(0); -- SP <= FP
debug_o <= "00011011";
Adebug_o <= "00011011";

when state_execute_ret_2 =>

Expand All @@ -994,19 +998,19 @@ BEGIN
state <= state_load_memcycle;

regfile(1) <= sp_plus_offset; -- SP+=4
debug_o <= "00011100";
Adebug_o <= "00011100";

when state_execute_ret_3 =>

PC <= data_bswap;
state <= state_fetch_pre;
regfile(1) <= sp_plus_offset; -- SP+=8
debug_o <= "00011101";
Adebug_o <= "00011101";

when state_execute_alu2 =>

state <= state_execute_alu2_wait;
debug_o <= "00011110";
Adebug_o <= "00011110";

when state_execute_alu2_wait =>

Expand All @@ -1019,7 +1023,7 @@ BEGIN
state <= state_fetch_pre;

end if;
debug_o <= "00011111";
Adebug_o <= "00011111";

when state_execute_swi =>

Expand All @@ -1032,26 +1036,27 @@ BEGIN
-- Store the SWI number in sr3.
sregfile(3) <= operand_A;
state <= state_fetch_pre;
debug_o <= "00100000";
Adebug_o <= "00100000";
null;

when state_error =>

-- write (l, String'("BAD"));
-- writeline (output, l);
-- stay in error state
debug_o <= "00100001";
Adebug_o <= "00100001";
Null;

when state_execute_brk =>
-- write (l, String'("BRK"));
-- writeline (output, l);
debug_o <= "00100010";
Adebug_o <= "00100010";
null;

when state_execute_bad =>
debug_o <= "00100100";
Adebug_o <= "00100100";
state <= state;
-- state <= state_fetch_pre;

when state_execute_gsr =>

Expand All @@ -1060,22 +1065,22 @@ BEGIN

-- Continue with next instruction
state <= state_fetch_pre;
debug_o <= "00100101";
Adebug_o <= "00100101";

when state_execute_ssr =>

sregfile(to_integer(unsigned(operand_B))) <= reg_A_value;

-- Continue with next instruction
state <= state_fetch_pre;
debug_o <= "00010110";
Adebug_o <= "00010110";

when others =>

-- What the?
-- state <= state_error;
state <= state;
debug_o <= "00100011";
Adebug_o <= "00100011";

end case;
end if;
Expand Down

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