Include official Armbian patches for 5.15 edge

patch/kernel/station-edge/2-0037-drm-sun4i-mixer-Add-caching-support.patch

@@ -0,0 +1,38 @@
+From 2e5d4ca1c07ddf06f8c3b18fd73baea7ce711169 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sun, 19 Jul 2020 11:37:41 +0200
+Subject: [PATCH 37/44] drm/sun4i: mixer: Add caching support
+
+Most registers are not safe to read out so enable cache in regmap.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -346,11 +346,23 @@ static const struct sunxi_engine_ops sun
+ 	.layers_init	= sun8i_layers_init,
+ };
+
++static bool sun8i_mixer_volatile_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case SUN8I_MIXER_GLOBAL_STATUS:
++	case SUN8I_MIXER_GLOBAL_DBUFF:
++		return true;
++	}
++	return false;
++}
++
+ static const struct regmap_config sun8i_mixer_regmap_config = {
++	.cache_type	= REGCACHE_FLAT,
+ 	.reg_bits	= 32,
+ 	.val_bits	= 32,
+ 	.reg_stride	= 4,
+ 	.max_register	= 0xffffc, /* guessed */
++	.volatile_reg	= sun8i_mixer_volatile_reg,
+ };
+
+ static int sun8i_mixer_of_get_id(struct device_node *node)

patch/kernel/station-edge/2-0041-arm64-dts-h6-deinterlace.patch

@@ -0,0 +1,30 @@
+From c009b3b707bbde30fa6ff49ca3075160524ea7b9 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Tue, 26 May 2020 20:08:27 +0200
+Subject: [PATCH 41/44] arm64: dts: h6 deinterlace
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -153,6 +153,17 @@
+ 			};
+ 		};
+
++		deinterlace: deinterlace@1420000 {
++			compatible = "allwinner,sun50i-h6-deinterlace";
++			reg = <0x01420000 0x2000>;
++			clocks = <&ccu CLK_BUS_DEINTERLACE>,
++				 <&ccu CLK_DEINTERLACE>,
++				 <&ccu CLK_MBUS_DEINTERLACE>;
++			clock-names = "bus", "mod", "ram";
++			resets = <&ccu RST_BUS_DEINTERLACE>;
++			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
+ 		video-codec@1c0e000 {
+ 			compatible = "allwinner,sun50i-h6-video-engine";
+ 			reg = <0x01c0e000 0x2000>;

patch/kernel/station-edge/megous/2-drm-panel-st7703-Improve-the-power-up-sequence-of-th.patch

@@ -0,0 +1,73 @@
+From 5d755224c15b01894aa74574450da632dd9a7ad1 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Sun, 5 Jul 2020 16:00:16 +0200
+Subject: [PATCH 294/467] drm/panel: st7703: Improve the power up sequence of
+ the panel
+
+The datasheet specifies that it's better to keep reset asserted
+while powering up the supplies, and that IOVCC should be enabled
+first.
+
+There also needs to be a delay after enabling the supplies and
+before deasserting the reset. The datasheet specifies 1ms after
+the supplies reach the required voltage. Use 10-20ms to give the
+power supplies some time to reach the required voltage, too.
+
+This fixes panel initialization failures during resume from sleep
+on PinePhone.
+
+Signed-off-by: Ondrej Jirman <megous@megous.com>
+---
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 25 ++++++++++---------
+ 1 file changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 9a34368f1..832c9aec0 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -425,29 +425,30 @@ static int st7703_prepare(struct drm_panel *panel)
+ 		return 0;
+
+ 	dev_dbg(ctx->dev, "Resetting the panel\n");
+-	ret = regulator_enable(ctx->vcc);
++	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
++
++	ret = regulator_enable(ctx->iovcc);
+ 	if (ret < 0) {
+-		dev_err(ctx->dev, "Failed to enable vcc supply: %d\n", ret);
++		dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
+ 		return ret;
+ 	}
+-	ret = regulator_enable(ctx->iovcc);
++
++	ret = regulator_enable(ctx->vcc);
+ 	if (ret < 0) {
+-		dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
+-		goto disable_vcc;
++		dev_err(ctx->dev, "Failed to enable vcc supply: %d\n", ret);
++		regulator_disable(ctx->iovcc);
++		return ret;
+ 	}
+
+-	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+-	usleep_range(20, 40);
++	/* Give power supplies time to stabilize before deasserting reset. */
++	usleep_range(10000, 20000);
++
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+-	msleep(20);
++	usleep_range(15000, 20000);
+
+ 	ctx->prepared = true;
+
+ 	return 0;
+-
+-disable_vcc:
+-	regulator_disable(ctx->vcc);
+-	return ret;
+ }
+
+ static int st7703_get_modes(struct drm_panel *panel,
+-- 
+2.34.0
+

patch/kernel/station-edge/megous/2-soc-rockchip-fix-usb3otg-port-on-rk3566.patch

@@ -0,0 +1,54 @@
+From 839e74b618618895a1765f850e5d4f3528806397 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Thu, 16 Sep 2021 17:47:10 +0200
+Subject: [PATCH 420/467] soc: rockchip: fix usb3otg port on rk3566
+
+The usb3otg port defaults to using the usb3phy clock, which isn't
+available on the rk3566 (due to the usb3phy being physically missing).
+
+We need to switch to the usb2phy clock for the usb3otg controller to
+function.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
+index 494cf2b5b..3aebb2588 100644
+--- a/drivers/soc/rockchip/grf.c
++++ b/drivers/soc/rockchip/grf.c
+@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk3399_grf __initconst = {
+ 	.num_values = ARRAY_SIZE(rk3399_defaults),
+ };
+
++#define RK3566_GRF_USB3OTG0_CON1	0x0104
++
++static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
++	{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
++	{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
++	{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
++};
++
++static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
++	.values = rk3566_defaults,
++	.num_values = ARRAY_SIZE(rk3566_defaults),
++};
++
++
+ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
+ 	{
+ 		.compatible = "rockchip,rk3036-grf",
+@@ -130,6 +144,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
+ 	}, {
+ 		.compatible = "rockchip,rk3399-grf",
+ 		.data = (void *)&rk3399_grf,
++	}, {
++		.compatible = "rockchip,rk3566-pipegrf",
++		.data = (void *)&rk3566_pipegrf,
+ 	},
+ 	{ /* sentinel */ },
+ };
+-- 
+2.34.0
+