Get Ready for AIC3104 Audio Cape and Clean Audio Patches

This patch cleans out audio patches that were never
applied and adds patches for McASP and Davinci EVM
to get ready for the AIC3104 Audio Cape.

patch.sh

@@ -24,7 +24,7 @@ EXTERNAL_TREE="git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable
 EXTERNAL_BRANCH="linux-3.8.y"
 EXTERNAL_SHA="dbf932a9b316d5b29b3e220e5a30e7a165ad2992"
 
-PATCHSET="dma rtc pinctrl cpufreq adc i2c da8xx-fb pwm mmc crypto 6lowpan capebus arm omap omap_sakoman omap_beagle_expansion omap_beagle omap_panda net drm not-capebus pru usb PG2 reboot iio w1 gpmc mxt ssd130x build hdmi resetctrl camera resources pmic pps leds capes fixes"
+PATCHSET="dma rtc pinctrl cpufreq adc i2c da8xx-fb pwm mmc crypto 6lowpan capebus arm omap omap_sakoman omap_beagle_expansion omap_beagle omap_panda net drm not-capebus pru usb PG2 reboot iio w1 gpmc mxt ssd130x build hdmi audio resetctrl camera resources pmic pps leds capes fixes"
 
 git_kernel_stable () {
 	git pull git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git master --tags || true

patches/audio/0002-ASoc-Davinci-EVM-Config-12MHz-CLK-for-AIC3x-Codec.patch

@@ -0,0 +1,49 @@
+From 887cbba2db4a9333db46f325ed12ae37fa658c18 Mon Sep 17 00:00:00 2001
+From: Cody Lacey <clacey@ti.com>
+Date: Fri, 18 Oct 2013 12:31:38 -0500
+Subject: [PATCH 1/2] ASoc: Davinci-EVM: Config 12MHz CLK for AIC3x Codec
+
+The AIC3x Codec needs a 12MHz clock source.  If the
+codec MCLK is connected to McASP AHCLKX or AHCLKR
+then the 24MHz internal clock needs to be divided
+by 2.
+---
+ sound/soc/davinci/davinci-evm.c |    8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
+index 421feb0..1d9e9ce 100644
+--- a/sound/soc/davinci/davinci-evm.c
++++ b/sound/soc/davinci/davinci-evm.c
+@@ -145,7 +145,7 @@ static const struct snd_soc_dapm_route audio_map[] = {
+ 	{"LINE2R", NULL, "Line In"},
+ };
+
+-/* Logic for a aic3x as connected on a davinci-evm */
++/* Logic for a tda998x as connected on a davinci-evm */
+ static int evm_tda998x_init(struct snd_soc_pcm_runtime *rtd)
+ {
+ 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+@@ -175,6 +175,7 @@ static int evm_tda998x_init(struct snd_soc_pcm_runtime *rtd)
+ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
+ {
+ 	struct snd_soc_codec *codec = rtd->codec;
++	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ 	struct snd_soc_dapm_context *dapm = &codec->dapm;
+ 	struct device_node *np = codec->card->dev->of_node;
+ 	int ret;
+@@ -193,6 +194,11 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
+ 		snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+ 	}
+
++	/* Divide McASP MCLK by 2 to provide 12MHz to codec */
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 2);
++	if (ret < 0)
++		return ret;
++
+ 	/* not connected */
+ 	snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
+ 	snd_soc_dapm_disable_pin(dapm, "HPLCOM");
+-- 
+1.7.9.5
+

patches/audio/0003-ASoc-McASP-Lift-Reset-on-CLK-Dividers-when-RX-TX.patch

@@ -0,0 +1,69 @@
+From a01f9e2ead2fcebc3dbb54488f2bc577f5fecd38 Mon Sep 17 00:00:00 2001
+From: Cody Lacey <clacey@ti.com>
+Date: Fri, 18 Oct 2013 12:42:00 -0500
+Subject: [PATCH 2/2] ASoc: McASP: Lift Reset on CLK Dividers when RX/TX
+
+If TX/RX CLK or High Frequency TX/RX CLK are set to
+output and they use the internally generated clock.
+Do not reset the tx/rx clock divider when receiving
+or sending data in case they supply the clock source
+for another device.
+---
+ sound/soc/davinci/davinci-mcasp.c |   34 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
+index 83232c6..7f36228 100644
+--- a/sound/soc/davinci/davinci-mcasp.c
++++ b/sound/soc/davinci/davinci-mcasp.c
+@@ -347,6 +347,23 @@ static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
+
+ static void mcasp_start_rx(struct davinci_audio_dev *dev)
+ {
++	u32 pdir = mcasp_get_reg(dev->base + DAVINCI_MCASP_PDIR_REG);
++	u32 thclk_reg = mcasp_get_reg(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG);
++	u32 tclk_reg = mcasp_get_reg(dev->base + DAVINCI_MCASP_ACLKXCTL_REG);
++
++	/*
++	*  If Transmit CLK or High Frequency Transmit CLK are set to output
++	*  and they use the internally generated clock. Do not reset the
++	*  transmit clock divider when receiving data in case they supply
++	*  the clock source for another device.
++	*/
++	if((pdir & ACLKX) && (tclk_reg & ACLKXE)) {
++		mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
++	}
++
++	if((pdir & AHCLKX) && (thclk_reg & AHCLKXE)) {
++		mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
++	}
+ 	mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
+ 	mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
+ 	mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
+@@ -364,6 +381,23 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev)
+ {
+ 	u8 offset = 0, i;
+ 	u32 cnt;
++	u32 pdir = mcasp_get_reg(dev->base + DAVINCI_MCASP_PDIR_REG);
++	u32 rhclk_reg = mcasp_get_reg(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG);
++	u32 rclk_reg = mcasp_get_reg(dev->base + DAVINCI_MCASP_ACLKRCTL_REG);
++
++	/*
++	*  If Receive CLK or High Frequency Receive CLK are set to output
++	*  and they use the internally generated clock. Do not reset the
++	*  receive clock divider when transmitting data in case they supply
++	*  the clock source for another device.
++	*/
++	if((pdir & ACLKR) && (rclk_reg & ACLKRE)) {
++		mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, RXCLKRST);
++	}
++
++	if((pdir & AHCLKR) && (rhclk_reg & AHCLKRE)) {
++		mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, RXHCLKRST);
++	}
+
+ 	mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
+ 	mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
+-- 
+1.7.9.5
+