An Architecture definition to generate instruction for a TuringTumble board.

I already tried, back in June 2019 to do that, unfortunately, I have no idea anymore what I tried.

So this time I'll start with some documentation.

There is this video from Claire @oe1cxw on Youtube: https://www.youtube.com/watch?v=XbwrOff59ck about defining custom archs for nextpnr.

And there is this 'simple' example architecture: https://github.com/YosysHQ/nextpnr/tree/master/generic/examples.

This directory did not changed much for the last three years.

It seems, however, that yosys must be tackled first.
Indeed, at first, we will need to synthetise Verilog code into TuringTumble cells.

So better start looking into the https://github.com/YosysHQ/yosys/blob/master/examples/cmos example directory, and see if we can define our cells there.

See TuringTumble.txt for a description of the board as an 'architecture'.

What you'll need:

* nextpnr-generic
* yosys

I need to get a grip on the problem first.
How about formally verifying some board solutions.

Ok, well, we're not formal yet ...
Clockless designs are pretty difficult to debug as everything is happening at once.
There is no way the trace can help unless we add delays in each of the `assign` statements.
Is that really a solution?

Now what?
I still have no geared-bit working as a struggle on the contact (wheel) interface.
Should it be inout or such ?

But, I do have enough to (ty to) run through yosys.
So at first, I need to extract the part I want to get synthetized (the 'pieces' from the puzzle.v file).
So, basically, two inputs (on top), few outputs (the bottom row), and maybe some internal states as extra outputs.