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Computer Engineering student at the University of São Paulo
|| Founder of AgroPoli || IPT TT-1
- São Paulo, São Paulo, Brazil
- https://lucasbertan.com.br/
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henriquegreg/RISC-V-Implementation-Verilog
henriquegreg/RISC-V-Implementation-Verilog PublicRepositório do grupo 3 (Grupo Cessar) de PCS3115
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