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Faster gdb memory access #380

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merged 2 commits into from
May 13, 2023
Merged

Faster gdb memory access #380

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55d27cb
kernel: riscv: use SUM bit for debug visibility
xobs May 11, 2023
b0ecc26
kernel: gdb: batch 2- and 4-byte accesses
xobs May 11, 2023
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60 changes: 31 additions & 29 deletions kernel/src/arch/riscv/mem.rs
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
// SPDX-FileCopyrightText: 2020 Sean Cross <sean@xobs.io>
// SPDX-License-Identifier: Apache-2.0

use crate::mem::MemoryManager;
use crate::arch::process::InitialProcess;
use crate::mem::MemoryManager;
use core::fmt;
use riscv::register::satp;
use riscv::register::{satp, sstatus};
use xous_kernel::{MemoryFlags, PID};

// pub const DEFAULT_STACK_TOP: usize = 0x8000_0000;
Expand Down Expand Up @@ -32,10 +32,7 @@ extern "C" {
}

unsafe fn zeropage(s: *mut u32) {
let page = core::slice::from_raw_parts_mut(
s,
PAGE_SIZE / core::mem::size_of::<u32>()
);
let page = core::slice::from_raw_parts_mut(s, PAGE_SIZE / core::mem::size_of::<u32>());
page.fill(0);
}

Expand Down Expand Up @@ -356,8 +353,7 @@ impl MemoryMapping {

// Zero-out the new page
let page_addr = l0pt_virt as *mut usize;
unsafe { zeropage(page_addr as *mut u32)
};
unsafe { zeropage(page_addr as *mut u32) };
}

let l0_pt = &mut unsafe { &mut (*(l0pt_virt as *mut LeafPageTable)) };
Expand Down Expand Up @@ -457,7 +453,7 @@ pub fn hand_page_to_user(virt: *mut u8) -> Result<(), xous_kernel::Error> {
Ok(())
}

#[cfg(feature="gdb-stub")]
#[cfg(feature = "gdb-stub")]
pub fn peek_memory<T>(addr: *mut T) -> Result<T, xous_kernel::Error> {
let virt = addr as usize;
let vpn1 = (virt >> 22) & ((1 << 10) - 1);
Expand All @@ -483,26 +479,27 @@ pub fn peek_memory<T>(addr: *mut T) -> Result<T, xous_kernel::Error> {
return Err(xous_kernel::Error::BadAddress);
}

// Ensure the entry hasn't already been mapped.
if l0_pt.entries[vpn0] & 1 == 0 {
// Ensure the entry has already been mapped, and that we're allowed
// to read it.
if l0_pt.entries[vpn0] & (MMUFlags::R | MMUFlags::VALID).bits()
!= (MMUFlags::R | MMUFlags::VALID).bits()
{
return Err(xous_kernel::Error::BadAddress);
}

// Strip the USER flag to the entry so we can read it
l0_pt.entries[vpn0] &= !MMUFlags::USER.bits();
unsafe { flush_mmu() };
// Enable supervisor access to user mode
unsafe { sstatus::set_sum() };

// Perform the read
let val = unsafe { addr.read_volatile() };

// Add the USER flag back to the entry
l0_pt.entries[vpn0] |= MMUFlags::USER.bits();
unsafe { flush_mmu() };
// Remove supervisor access to user mode
unsafe { sstatus::clear_sum() };

Ok(val)
}

#[cfg(feature="gdb-stub")]
#[cfg(feature = "gdb-stub")]
pub fn poke_memory<T>(addr: *mut T, val: T) -> Result<(), xous_kernel::Error> {
let virt = addr as usize;
let vpn1 = (virt >> 22) & ((1 << 10) - 1);
Expand All @@ -528,30 +525,35 @@ pub fn poke_memory<T>(addr: *mut T, val: T) -> Result<(), xous_kernel::Error> {
return Err(xous_kernel::Error::BadAddress);
}

// Ensure the entry hasn't already been mapped.
if l0_pt.entries[vpn0] & 1 == 0 {
// Ensure the entry has been mapped.
if l0_pt.entries[vpn0] & MMUFlags::VALID.bits() == 0 {
return Err(xous_kernel::Error::BadAddress);
}

// Ensure we're allowed to read it.
let was_writable = l0_pt.entries[vpn0] & MMUFlags::W.bits() != 0;

// Strip the USER flag to the entry so we can read it
l0_pt.entries[vpn0] &= !MMUFlags::USER.bits();
l0_pt.entries[vpn0] |= MMUFlags::W.bits();
unsafe { flush_mmu() };
// Add the WRITE bit, which allows us to patch things like
// program code.
if !was_writable {
l0_pt.entries[vpn0] |= MMUFlags::W.bits();
unsafe { flush_mmu() };
}

// Enable supervisor access to user mode
unsafe { sstatus::set_sum() };

// Perform the write
unsafe { addr.write_volatile(val) };

// Add the USER flag back to the entry
l0_pt.entries[vpn0] |= MMUFlags::USER.bits();
// Remove supervisor access to user mode
unsafe { sstatus::clear_sum() };

// Strip the "writable" bit if it wasn't set before
// Remove the WRITE bit if it wasn't previously set
if !was_writable {
l0_pt.entries[vpn0] &= !MMUFlags::W.bits();
unsafe { flush_mmu() };
}
unsafe { flush_mmu() };

Ok(())
}
Expand Down Expand Up @@ -889,7 +891,7 @@ pub fn virt_to_phys(virt: usize) -> Result<usize, xous_kernel::Error> {

pub fn ensure_page_exists_inner(address: usize) -> Result<usize, xous_kernel::Error> {
// Disallow mapping memory outside of user land
if ! MemoryMapping::current().is_kernel() && address >= USER_AREA_END {
if !MemoryMapping::current().is_kernel() && address >= USER_AREA_END {
return Err(xous_kernel::Error::OutOfMemory);
}
let virt = address & !0xfff;
Expand Down
54 changes: 43 additions & 11 deletions kernel/src/debug/gdb/multi_thread_base.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ use gdbstub::target::ext::base::single_register_access::SingleRegisterAccessOps;
use gdbstub::target::TargetResult;

use super::XousTarget;
use core::convert::TryInto;

impl MultiThreadBase for XousTarget {
fn read_registers(
Expand Down Expand Up @@ -107,10 +108,33 @@ impl MultiThreadBase for XousTarget {
.unwrap()
.activate()
.unwrap();
for (offset, b) in data.iter_mut().enumerate() {
*b = crate::arch::mem::peek_memory((current_addr + offset) as *mut u8)
.unwrap_or(0xff);
// println!("<< Peek {:02x} @ {:08x}", *b, current_addr);

if data.len() == 2 && (start_addr & 1) == 0 {
let val = crate::arch::mem::peek_memory(start_addr as *mut u16).unwrap_or(0);
for (dest, src) in data.iter_mut().zip(val.to_le_bytes()) {
*dest = src;
}
} else if data.len() == 4 && (start_addr & 3) == 0 {
let val = crate::arch::mem::peek_memory(start_addr as *mut u32).unwrap_or(0);
for (dest, src) in data.iter_mut().zip(val.to_le_bytes()) {
*dest = src;
}
} else if (data.len() & 3) == 0 && (start_addr & 3) == 0 {
let mut current_addr = current_addr;
for word in data.chunks_mut(4) {
let bytes = crate::arch::mem::peek_memory(current_addr as *mut u32)
.unwrap_or(0)
.to_le_bytes();
for (dest, src) in word.iter_mut().zip(bytes) {
*dest = src;
}
current_addr += 4;
}
} else {
for (offset, b) in data.iter_mut().enumerate() {
*b = crate::arch::mem::peek_memory((current_addr + offset) as *mut u8)
.unwrap_or(0xff);
}
}

// Restore the previous PID
Expand Down Expand Up @@ -145,13 +169,21 @@ impl MultiThreadBase for XousTarget {
.unwrap()
.activate()
.unwrap();
data.iter().for_each(|b| {
if let Err(_e) = crate::arch::mem::poke_memory(current_addr as *mut u8, *b) {
// panic!("couldn't poke memory: {:?}", _e);
}
// println!("Poked {:02x} @ {:08x}", *b, current_addr);
current_addr += 1;
});

if data.len() == 2 && (start_addr & 1) == 0 {
let val = u16::from_le_bytes(data.try_into().unwrap());
crate::arch::mem::poke_memory(start_addr as *mut u16, val).ok();
} else if data.len() == 4 && (start_addr & 3) == 0 {
let val = u32::from_le_bytes(data.try_into().unwrap());
crate::arch::mem::poke_memory(start_addr as *mut u32, val).ok();
} else {
data.iter().for_each(|b| {
if let Err(_e) = crate::arch::mem::poke_memory(current_addr as *mut u8, *b) {
// panic!("couldn't poke memory: {:?}", _e);
}
current_addr += 1;
});
}

// Restore the previous PID
system_services
Expand Down