tests/linux: add a RaptorLake hybrid test

6 big HT cores, with private L2. 8 small non-HT cores, with L2 shared by 4. Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr> (cherry picked from commit eda8f63)
bgoglin · Nov 21, 2023 · 33d96ff · 33d96ff
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diff --git a/tests/hwloc/linux/20em64t-hybrid-1p6c2t+2ca4co1t.output b/tests/hwloc/linux/20em64t-hybrid-1p6c2t+2ca4co1t.output
@@ -0,0 +1,90 @@
+Machine (P#0 total=32489480KB DMIProductName="HP EliteBook 840 14 inch G10 Notebook PC" DMIProductVersion= DMIBoardVendor=HP DMIBoardName=8B41 DMIBoardVersion="KBC Version 51.32.00" DMIBoardAssetTag= DMIChassisVendor=HP DMIChassisType=10 DMIChassisVersion= DMIChassisAssetTag= DMIBIOSVendor=HP DMIBIOSVersion="V70 Ver. 01.02.03" DMIBIOSDate=09/13/2023 DMISysVendor=HP Backend=Linux OSName=Linux OSRelease=6.1.0-13-amd64 OSVersion="#1 SMP PREEMPT_DYNAMIC Debian 6.1.55-1 (2023-09-29)" HostName=vesubie Architecture=x86_64)
+  Package L#0 (P#0 total=32489480KB CPUVendor=GenuineIntel CPUFamilyNumber=6 CPUModelNumber=186 CPUModel="13th Gen Intel(R) Core(TM) i7-1370P" CPUStepping=2)
+    NUMANode L#0 (P#0 local=32489480KB total=32489480KB)
+    L3Cache L#0 (P#0 size=24576KB linesize=64 ways=12)
+      L2Cache L#0 (P#0 size=1280KB linesize=64 ways=10)
+        L1dCache L#0 (P#0 size=48KB linesize=64 ways=12)
+          L1iCache L#0 (P#0 size=32KB linesize=64 ways=8)
+            Core L#0 (P#0)
+              PU L#0 (P#0)
+              PU L#1 (P#1)
+      L2Cache L#1 (P#1 size=1280KB linesize=64 ways=10)
+        L1dCache L#1 (P#4 size=48KB linesize=64 ways=12)
+          L1iCache L#1 (P#4 size=32KB linesize=64 ways=8)
+            Core L#1 (P#4)
+              PU L#2 (P#2)
+              PU L#3 (P#3)
+      L2Cache L#2 (P#2 size=1280KB linesize=64 ways=10)
+        L1dCache L#2 (P#8 size=48KB linesize=64 ways=12)
+          L1iCache L#2 (P#8 size=32KB linesize=64 ways=8)
+            Core L#2 (P#8)
+              PU L#4 (P#4)
+              PU L#5 (P#5)
+      L2Cache L#3 (P#3 size=1280KB linesize=64 ways=10)
+        L1dCache L#3 (P#12 size=48KB linesize=64 ways=12)
+          L1iCache L#3 (P#12 size=32KB linesize=64 ways=8)
+            Core L#3 (P#12)
+              PU L#6 (P#6)
+              PU L#7 (P#7)
+      L2Cache L#4 (P#4 size=1280KB linesize=64 ways=10)
+        L1dCache L#4 (P#16 size=48KB linesize=64 ways=12)
+          L1iCache L#4 (P#16 size=32KB linesize=64 ways=8)
+            Core L#4 (P#16)
+              PU L#8 (P#8)
+              PU L#9 (P#9)
+      L2Cache L#5 (P#5 size=1280KB linesize=64 ways=10)
+        L1dCache L#5 (P#20 size=48KB linesize=64 ways=12)
+          L1iCache L#5 (P#20 size=32KB linesize=64 ways=8)
+            Core L#5 (P#20)
+              PU L#10 (P#10)
+              PU L#11 (P#11)
+      L2Cache L#6 (P#6 size=2048KB linesize=64 ways=16)
+        L1dCache L#6 (P#24 size=32KB linesize=64 ways=8)
+          L1iCache L#6 (P#24 size=64KB linesize=64 ways=8)
+            Core L#6 (P#24)
+              PU L#12 (P#12)
+        L1dCache L#7 (P#25 size=32KB linesize=64 ways=8)
+          L1iCache L#7 (P#25 size=64KB linesize=64 ways=8)
+            Core L#7 (P#25)
+              PU L#13 (P#13)
+        L1dCache L#8 (P#26 size=32KB linesize=64 ways=8)
+          L1iCache L#8 (P#26 size=64KB linesize=64 ways=8)
+            Core L#8 (P#26)
+              PU L#14 (P#14)
+        L1dCache L#9 (P#27 size=32KB linesize=64 ways=8)
+          L1iCache L#9 (P#27 size=64KB linesize=64 ways=8)
+            Core L#9 (P#27)
+              PU L#15 (P#15)
+      L2Cache L#7 (P#7 size=2048KB linesize=64 ways=16)
+        L1dCache L#10 (P#28 size=32KB linesize=64 ways=8)
+          L1iCache L#10 (P#28 size=64KB linesize=64 ways=8)
+            Core L#10 (P#28)
+              PU L#16 (P#16)
+        L1dCache L#11 (P#29 size=32KB linesize=64 ways=8)
+          L1iCache L#11 (P#29 size=64KB linesize=64 ways=8)
+            Core L#11 (P#29)
+              PU L#17 (P#17)
+        L1dCache L#12 (P#30 size=32KB linesize=64 ways=8)
+          L1iCache L#12 (P#30 size=64KB linesize=64 ways=8)
+            Core L#12 (P#30)
+              PU L#18 (P#18)
+        L1dCache L#13 (P#31 size=32KB linesize=64 ways=8)
+          L1iCache L#13 (P#31 size=64KB linesize=64 ways=8)
+            Core L#13 (P#31)
+              PU L#19 (P#19)
+depth 0:           1 Machine (type #0)
+ depth 1:          1 Package (type #1)
+  depth 2:         1 L3Cache (type #6)
+   depth 3:        8 L2Cache (type #5)
+    depth 4:       14 L1dCache (type #4)
+     depth 5:      14 L1iCache (type #9)
+      depth 6:     14 Core (type #2)
+       depth 7:    20 PU (type #3)
+Special depth -3:  1 NUMANode (type #13)
+CPU kind #0 efficiency 0 cpuset 0x000ff000
+  FrequencyMaxMHz = 3900
+  FrequencyBaseMHz = 1400
+CPU kind #1 efficiency 1 cpuset 0x00000fff
+  FrequencyMaxMHz = 5000
+  FrequencyBaseMHz = 1900
+Topology not from this system
diff --git a/tests/hwloc/linux/20em64t-hybrid-1p6c2t+2ca4co1t.tar.bz2 b/tests/hwloc/linux/20em64t-hybrid-1p6c2t+2ca4co1t.tar.bz2
diff --git a/tests/hwloc/linux/Makefile.am b/tests/hwloc/linux/Makefile.am
@@ -57,6 +57,7 @@ sysfs_outputs = \
 		128arm-2pa2n8cluster4co.output \
 		256ia64-64n2s2c.output \
 		2s390-2c.output \
+		20em64t-hybrid-1p6c2t+2ca4co1t.output \
 		20s390-2g6s4c.output \
 		2arm-2c.output \
 		nvidiagpunumanodes.output \
@@ -128,6 +129,7 @@ sysfs_tarballs = \
 		128arm-2pa2n8cluster4co.tar.bz2 \
 		256ia64-64n2s2c.tar.bz2 \
 		2s390-2c.tar.bz2 \
+		20em64t-hybrid-1p6c2t+2ca4co1t.tar.bz2 \
 		20s390-2g6s4c.tar.bz2 \
 		2arm-2c.tar.bz2 \
 		2pa-pcidomain32bits.tar.bz2 \