Minor sync-up with Piccolo

bluespec · Jan 22, 2019 · 8eb1115 · 8eb1115
1 parent 5f7bebc
commit 8eb1115
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Showing 2 changed files with 9 additions and 3 deletions.
diff --git a/src_SSITH_P2/README.txt b/src_SSITH_P2/README.txt
@@ -29,3 +29,9 @@ into this socket:
     - Variations/alternatives by various SSITH project teams
 
 >================================================================
+Whenever there are changes to the Piccolo core, rerun:
+
+  $ make compile
+  $ cp Verilog_RTL/* xilinx_ip/hdl/
+
+>================================================================
diff --git a/src_Testbench/SoC/SoC_Map.bsv b/src_Testbench/SoC/SoC_Map.bsv
@@ -100,10 +100,10 @@ module mkSoC_Map (SoC_Map_IFC);
    endfunction
 
    // ----------------------------------------------------------------
-   // Near_Mem_IO (CLINT)
+   // Near_Mem_IO (including CLINT, the core-local interruptor)
 
-   Fabric_Addr near_mem_io_addr_base = 'h_6300_0000;
-   Fabric_Addr near_mem_io_addr_size = 'h_0001_0000;    // 64K
+   Fabric_Addr near_mem_io_addr_base = 'h_0200_0000;
+   Fabric_Addr near_mem_io_addr_size = 'h_0000_C000;    // 48K
    Fabric_Addr near_mem_io_addr_lim  = near_mem_io_addr_base + near_mem_io_addr_size;
 
    function Bool fn_is_near_mem_io_addr (Fabric_Addr addr);