RISC-V Debug Module

Contents

• 1. A RISC-V Debug Module

1. A RISC-V Debug Module

This repository contains an implementation of a Debug Module for RISC-V processors, following the RISC-V standard "External Debug Support" spec:

RISC-V External Debug Support
Version 0.13.2
d5029366d59e8563c08b6b9435f82573b603e48e
Fri Mar 22 09:06:04 2019 -0700

The above spec is independent of any particular implementation of the Debug Module (or RISC-V CPU that it controls). It just specifies the standard registers in the Debug Module that can be read and written by an external debugger (such as GDB). It specifies the address map of these registers, and the semantics, i.e., what happens (examining or manipulating a RISC-V CPU) when one reads or writes these registers.

This repo is one such implementation. The top-level module is Debug_Module.bsv and has more comments with implementation details. Note: for reading/writing RISC-V memory, the Debug Module spec allows two alternate mechanisms, a “System Bus Access” mechanism and a “Program Buffer” mechanism. This implementation only provides the former, via an AXI4 interface.

The Debug Module is fully synthesizable, and we have used it on FPGAs and in simulation for many years, with many RISC-V CPUs, including Magritte, Piccolo, Flute, Toooba (all free and open-source, see links for details).

This implementation is written in the HLHDL (High-Level Hardware Description Language) BSV. A free, open-source compiler to Verilog can be found here, so the generated RTL can be incorporated into RISC-V CPU designs written in any HDL, such as Verilog, SystemVerilog, VHDL or other.

Facing the debugger (e.g., GDB), we have connected the DMI (Debug Module Interface) to GDB both via OpenOCD and via our own gdbstub (free, open-source, written in C). We have implemented the connection between the Debug Module and OpenOCD/gdbstub both using JTAG (on FPGAs) and with TCP/IP (for simulation). Please contact us if you need details.

Facing the RISC-V CPU, it has simple FIFO-like request/response interfaces to the CPU for run-control (run, continue, halt, step) and to read/write GPRs, FPRs and CSRs. It has a simple AXI4 interface to read/write RISC-V memory.