fixed compilation with no EVEX

bochs-emu · Oct 16, 2023 · 221cac7 · 221cac7
1 parent a3d2fec
commit 221cac7
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Showing 2 changed files with 17 additions and 7 deletions.
diff --git a/bochs/cpu/cpuid.cc b/bochs/cpu/cpuid.cc
@@ -926,11 +926,13 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_ebx(Bit32u extra) const
 
   // [30:30]  AVX512BW instructions support
   // [31:31]  AVX512VL variable vector length support
+#if BX_SUPPORT_EVEX
   if (is_cpu_extension_supported(BX_ISA_AVX512)) {
     if (is_cpu_extension_supported(BX_ISA_AVX512_BW))
       ebx |= BX_CPUID_STD7_SUBLEAF0_EBX_AVX512BW;
     ebx |= BX_CPUID_STD7_SUBLEAF0_EBX_AVX512VL;
   }
+#endif
 
   return ebx;
 }
@@ -1056,8 +1058,12 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_edx(Bit32u extra) const
   //   [7:6]    reserved
 
   //   [8:8]    AVX512 VP2INTERSECT instructions support
-  if (is_cpu_extension_supported(BX_ISA_AVX512_VP2INTERSECT))
-    edx |= BX_CPUID_STD7_SUBLEAF0_EDX_AVX512_VPINTERSECT;
+#if BX_SUPPORT_EVEX
+  if (is_cpu_extension_supported(BX_ISA_AVX512)) {
+    if (is_cpu_extension_supported(BX_ISA_AVX512_VP2INTERSECT))
+      edx |= BX_CPUID_STD7_SUBLEAF0_EDX_AVX512_VPINTERSECT;
+  }
+#endif
 
   //   [9:9]    SRBDS_CTRL: IA32_MCU_OPT_CTRL MSR
   // * [10:10]  MD clear (SCA)
@@ -1122,8 +1128,12 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_subleaf_1_eax(Bit32u extra) const
     eax |= BX_CPUID_STD7_SUBLEAF1_EAX_AVX_VNNI;
 
   //   [5:5]    AVX512_BF16 conversion instructions support
-  if (is_cpu_extension_supported(BX_ISA_AVX512_BF16))
-    eax |= BX_CPUID_STD7_SUBLEAF1_EAX_AVX512_BF16;
+#if BX_SUPPORT_EVEX
+  if (is_cpu_extension_supported(BX_ISA_AVX512)) {
+    if (is_cpu_extension_supported(BX_ISA_AVX512_BF16))
+      eax |= BX_CPUID_STD7_SUBLEAF1_EAX_AVX512_BF16;
+  }
+#endif
 
   //   [6:6]    LASS: Linear Address Space Separation support
   if (is_cpu_extension_supported(BX_ISA_LASS))

diff --git a/bochs/cpu/decoder/features.h b/bochs/cpu/decoder/features.h
@@ -91,13 +91,13 @@ x86_feature(BX_ISA_SHA512, "sha512")                                    /* SHA-5
 x86_feature(BX_ISA_GFNI, "gfni")                                        /* GFNI instruction */
 x86_feature(BX_ISA_SM3, "sm3")                                          /* SM3 instruction */
 x86_feature(BX_ISA_SM4, "sm4")                                          /* SM4 instruction */
-#if BX_SUPPORT_EVEX
 x86_feature(BX_ISA_AVX512, "avx512")                                    /* AVX-512 instruction */
+x86_feature(BX_ISA_AVX512_DQ, "avx512dq")                               /* AVX-512DQ instruction */
+x86_feature(BX_ISA_AVX512_BW, "avx512bw")                               /* AVX-512 Byte/Word instruction */
+#if BX_SUPPORT_EVEX
 x86_feature(BX_ISA_AVX512_CD, "avx512cd")                               /* AVX-512 Conflict Detection instruction */
 x86_feature(BX_ISA_AVX512_PF, "avx512pf")                               /* AVX-512 Sparse Prefetch instruction */
 x86_feature(BX_ISA_AVX512_ER, "avx512er")                               /* AVX-512 Exponential/Reciprocal instruction */
-x86_feature(BX_ISA_AVX512_DQ, "avx512dq")                               /* AVX-512DQ instruction */
-x86_feature(BX_ISA_AVX512_BW, "avx512bw")                               /* AVX-512 Byte/Word instruction */
 x86_feature(BX_ISA_AVX512_VBMI, "avx512vbmi")                           /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
 x86_feature(BX_ISA_AVX512_VBMI2, "avx512vbmi2")                         /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
 x86_feature(BX_ISA_AVX512_IFMA52, "avx512ifma52")                       /* AVX-512 IFMA52 Instructions */